τAU: Timing Analysis under Uncertainty

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 615-620

  Bhardwaj, Sarvesh ^a   Vrudhula, Sarma B K ^a   Blaauw, David ^b  

^a UNIVERSITY OF ARIZONA   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BAYESIAN NETWORKS (BN); DIRECTED ACYCLIC GRAPHS (DAG);

COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; COMPUTER SIMULATION; GATEWAYS (COMPUTER NETWORKS); MONTE CARLO METHODS; NANOTECHNOLOGY; NUMERICAL METHODS; OXIDES; PROBABILITY DISTRIBUTIONS; RANDOM PROCESSES; STATISTICAL METHODS;

CMOS INTEGRATED CIRCUITS;

EID: 0347409182     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. http://www.ai.mit.edu/̃murphyk/software/bnt/bnt.html.
2. http://www.ece.arizona.edu/̃sarvesh/pubs.html
3. A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula. Statistical timing analysis using boounds and selective enumeration. In Workshop TAU, pages 332-337, Dec 2002.
4. S. Bhanja and N. Ranganathan. Dependency preserving probabilistic modeling of switching activity using bayesian networks. In Proc. of DAC, pages 209-214, 2001.
5. D. Boning and S. Nassif. Models of Process Variations in Device and Interconnect: In Design of High-Performance Microprocessor Circuits, A. Chandrakasan, 2000.
6. R. Cowell, A. P. Dawid, S. L. Lauritzen, and D. I. Spiegelhalter. Probabilistic Networks and Expert Systems. Springer, 1999.
7. S. E. Elmaghraby. Activity Networks: Project Planning and Control by Network Models. John Wiley & Sons, 1977.
8. F. V. Jensen. Bayesian Networks and Decision Graphs. Springer, 2000.
9. H.-F. Jyu, S. Malik, S. Devdas, and K. Keutzer. Statistical timing analysis of combinational logic circuits. IEEE Trans. on VLSI, 1(2):126-137, June 1993.
10. K. Keutzer and M. Orshansky. From blind certainty to informed uncertainty. In Workshop TAU, pages 37-41, Dec 2002.
11. J.-J. Liou, K.-T. Cheng, S. Kundu, and A. Krstic. Fast statistical timing analysis by probabilistic event propagation. In Proc. of DAC, pages 661-666, 2001.
12. J.-J. Liou, A. Krstic, W. L.-C., and K.-T. Cheng, False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. In Proc. of DAC, pages 566-569, 2002.
13. A. Nadas. Probabilistic pert. IBM J. Res. Develop, pages 339-347, May 1979.
14. A. Nardi, A. Neviani, E. Zanoni, M. Quarantelli, and C. Guardiani, Impact of unrealistic worst case modeling on the performance of vlsi circuits in deep submicron cmos technologies. Semiconductor Manufacturing, IEEE Transactions on, 12(4):396-402, Nov 1999.
15. M. Orshansky and K. Keutzer. A general probabilistic framework for worst case timing analysis. In Proc. of DAC, pages 556-561, 2002.
16. A. Papoulis. Probability, random variables, and stochastic processes. Mc-Graw Hill, 1965.
17. J. Pearl. Probabilistic Reasoning in Intelligent Systems: Networks of Plausible Inference. Morgan Kaufmann, 1938.
18. S. M. Ross. Stochastic processes. Wiley, 1996.