Border traps in Ge/III-V channel devices: Analysis and reliability aspects

IEEE Transactions on Device and Materials Reliability

Volumn 13, Issue 4, 2013, Pages 444-455

  Eddy Simoen, ^a   Lin, Dennis Han Chung ^a   Alian, A ^a   Brammertz, G ^a   Merckling, C ^a   Mitard, J ^a   Claeys, Cor ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Border traps; Germanium channel; High k oxide; III V channel; Low frequency noise

Indexed keywords

BORDER TRAPS; CHANNEL TRANSISTORS; HIGH-K OXIDES; III-V CHANNEL; LOW FREQUENCY (1/F) NOISE; LOW-FREQUENCY NOISE; MEASUREMENT TECHNIQUES; SEMICONDUCTOR STRUCTURE;

GERMANIUM;

RELIABILITY ANALYSIS;

EID: 84897810333     PISSN: 15304388     EISSN: 15582574     Source Type: Journal    
DOI: 10.1109/TDMR.2013.2275917     Document Type: Article

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