Interface and border traps in Ge-based gate stacks

ECS Transactions

Volumn 35, Issue 3, 2011, Pages 465-480

  Nyns, L ^a   Lin, D ^a   Brammertz, G ^a   Bellenger, F ^b   Shi, X ^a   Sioncke, S ^a   Van Elshocht, S ^a   Caymax, M ^a  

^a IMEC   (Belgium)

^b CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BORDER TRAPS; CRITICAL ISSUES; ELECTRICAL PASSIVATION; GATE STACKS; GE SURFACES; HIGH-K MATERIALS; HIGH-PERFORMANCE TECHNOLOGIES; INTERFACE TRAPS; INVERSE RELATIONS; POST-DEPOSITION ANNEAL;

ELECTRIC WIRE; GATE DIELECTRICS; GERMANIUM; GERMANIUM OXIDES; GRAPHENE; LOGIC GATES; NANOWIRES; PASSIVATION; SURFACES;

INTERFACES (MATERIALS);

EID: 79960795415     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3569938     Document Type: Conference Paper

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