A distributed model for border traps in Al2O3 - InGaAs MOS devices

IEEE Electron Device Letters

Volumn 32, Issue 4, 2011, Pages 485-487

  Yuan, Yu ^a   Wang, Lingquan ^a   Yu, Bo ^a   Shin, Byungha ^b   Ahn, Jaesoo ^b   McIntyre, Paul C ^b   Asbeck, Peter M ^a   Rodwell, Mark J W ^c   Taur, Yuan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Stanford University   (United States)

^c University of California   (United States)

Author keywords

Border trap; III V; MOS; tunneling

Indexed keywords

BORDER TRAPS; DISTRIBUTED CIRCUIT MODEL; DISTRIBUTED MODELS; FREQUENCY DEPENDENCE; FREQUENCY DISPERSION; III-V; LUMPED-CIRCUIT; MEASURED DATA; MODEL-BASED; MOS; QUANTITATIVE AGREEMENT; SEMI-CONDUCTOR SURFACES; TRAP STATE; TUNNELING; VOLUME DENSITY;

CAPACITANCE; DIELECTRIC FILMS; ELECTRIC CONDUCTIVITY; GATE DIELECTRICS; GATES (TRANSISTOR); LUMPED PARAMETER NETWORKS; MODELS; SEMICONDUCTING INDIUM;

MOS DEVICES;

EID: 79953043383     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2105241     Document Type: Article

References (12)

1. M. Passlack, R. Droopad, and G. Brammertz, "Suitability study of oxide/ gallium arsenide interfaces for MOSFET applications," IEEE Trans. Electron Devices, vol. 57, no. 11, pp. 2944-2956, Nov. 2010.
2. Y. Xuan, Y. Q. Wu, T. Shen, T. Yang, and P. D. Ye, "High performance submicron inversion-type enhancement-mode InGaAs MOSFETs with ALD Al2O3, HfO2 and HfAlO as gate dielectrics," in IEDM Tech. Dig., 2007, pp. 637-640.
3. N. Goel, P. Majhi, C. O. Chui,W. Tsai, D. Choi, and J. S. Harris, "InGaAs metal-oxide-semiconductor capacitors with HfO2 gate dielectric grown by atomic-layer deposition," Appl. Phys. Lett., vol. 89, no. 16, p. 163 517, Oct. 2006.
4. E. J. Kim, E. Chagarov, J. Cagnon, Y. Yuan, A. C. Kummel, P. M. Asbeck, S. Stemmer, K. C. Saraswat, and P. C. McIntyre, "Atomically abrupt and unpinned Al2O3/In0.53Ga0.47As interfaces: Experiment and simulation," J. Appl. Phys., vol. 106, no. 12, p. 124 508, Dec. 2009.
5. G. Brammertz, K. Martens, S. Sioncke, A. Delabie, M. Caymax, M. Meuris, and M. Heyns, "Characteristic trapping lifetime and capacitance-voltage measurements of GaAs metal-oxide-semiconductor structures," Appl. Phys. Lett., vol. 91, no. 13, p. 133 510, Sep. 2007.
6. E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology. New York: Wiley, 1982.
7. W. Shockley andW. T. Read, Jr., "Statistics of the recombinations of holes and electrons," Phys. Rev., vol. 87, no. 5, pp. 835-842, Sep. 1952.
8. F. P. Heiman and G. Warfield, "The effects of oxide traps on the MOS capacitance," IEEE Trans. Electron Devices, vol. ED-12, no. 4, pp. 167-178, Apr. 1965.
9. H. Preier, "Contribution of surface states to MOS impedance," Appl. Phys. Lett., vol. 10, no. 12, pp. 361-363, Jun. 1967.
10. D. S. L. Mui, J. Reed, D. Biswas, and H. Morkoç, "A new circuit model for tunneling related trapping at insulator-semiconductor interfaces in accumulation," J. Appl. Phys., vol. 72, no. 2, pp. 553-558, Jul. 1992.
11. A. D. Polyanin and V. F. Zaitsev, Handbook of Exact Solutions for Ordinary Differential Equations. Boca Raton, FL: CRC Press, 2003.
12. E. J. Kim, L. Wang, P. M. Asbeck, K. C. Saraswat, and P. C. McIntyre, "Border traps in Al2O3/In0.53Ga0.47As (100) gate stacks and their passivation by hydrogen anneals," Appl. Phys. Lett., vol. 96, no. 1, p. 012906, Jan. 2010.