Understanding and optimization of hot-carrier reliability in Germanium-on-Silicon pMOSFETs

IEEE Transactions on Electron Devices

Volumn 56, Issue 5, 2009, Pages 1063-1069

  Maji, Debabrata ^a   Crupi, Felice ^b   Amat, Esteve ^c   Simoen, Eddy ^d   De Jaeger, Brice ^d   Brunco, David P ^d,e   Manoj, C R ^a   Rao, V Ramgopal ^a   Magnone, Paolo ^b   Giusi, Gino ^b   Pace, Calogero ^b   Pantisano, Luigi ^d   Mitard, Jérôme ^d   Rodríguez, Rosana ^c   Nafría, Montserrat ^c  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b UNIVERSITY OF CALABRIA   (Italy)

^c UNIVERSITAT AUTÒNOMA DE BARCELONA   (Spain)

^d IMEC   (Belgium)

^e INTEL CORPORATION   (United States)

Author keywords

Germanium; High k; Hot carrier (HC); Impact ionization; Negative bias temperature instability (NBTI); pMOSFET

Indexed keywords

COMPREHENSIVE STUDIES; GERMANIUM ON SILICONS; HIGH-K; HOT CARRIER INJECTION; HOT CARRIER RELIABILITY; LIFETIME IMPROVEMENT; METAL GATE; MOSFETS; NEGATIVE BIAS TEMPERATURE INSTABILITY; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); P-MOSFETS; PMOSFET;

ELECTRIC CURRENTS; FIELD EFFECT TRANSISTORS; GERMANIUM; HOT CARRIERS; IMPACT IONIZATION; MONOLAYERS; NEGATIVE TEMPERATURE COEFFICIENT; PASSIVATION; SEMICONDUCTING SILICON COMPOUNDS; SILICON; THERMODYNAMIC STABILITY;

MOSFET DEVICES;

EID: 67349186858     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2015854     Document Type: Article

References (18)

1. C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, "A sub-400 °C germanium MOSFET technology with high-k dielectric and metal gate," in IEDM Tech. Dig., 2002, pp. 437-440.
2. 4 surface passivation," IEEE Electron Device Lett. vol. 25, no. 9, pp. 631-633, Sep. 2004.
3. P. Zimmerman, G. Nicholas, B. De Jaeger, B. Kaczer, A. Stesmans, L.-Å. Ragnarsson, D. P. Brunco, F. E. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. M. Heyns, "High performance Ge pMOS devices using Si-compatible process flow," in IEDM Tech. Dig., 2006, pp. 655-657.
4. G. Nicholas, B. D. Jaeger, D. P. Brunco, P. Zimmerman, G. Eneman, K. Martens, M. Meuris, and M. Heyns, "High-performance deep submicron Ge pMOSFETs with halo implants," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2503-2511, Sep. 2007.
5. J. Oh, P. Majhi, H. Lee, O. Yoo, S. Banerjee, C. Y. Kang, J.-W. Yang, R. Harris, H.-H. Tseng, and R. Jammy, "Improved electrical characteristics of Ge-on-Si field effect transistors with control Ge epitaxial layer thickness on Si substrates," IEEE Electron Device Lett., vol. 28, no. 11, pp. 1044-1046, Nov. 2007.
6. 3/AlN gate stacks," IEEE Electron Device Lett., vol. 28, no. 8, pp. 746-749, Aug. 2007.
7. D. P. Brunco, B. De Jaeger, G. Eneman, J. Mitard, G. Hellings, A. Satta, V. Terzieva, L. Souriau, F. E. Leys, G. Pourtois, M. Houssa, G. Winderickx, E. Vrancken, S. Sioncke, K. Opsomer, G. Nicholas, M. Caymax, A. Stesman, J. Van Steenbergen, P. W. Mertens, M. Meuris, and M. M. Heyns, "Germanium MOSFET devices: Advances in materials understanding, process development, and electrical performance," J. Electrochem. Soc., vol. 155, no. 7, pp. H552-H557, 2008.
8. E. Simoen, E. Voroshazi, J. Mitard, G. Eneman, D. P. Brunco, B. De Jaeger, and M. Meuris, "Substrate bias effect on Ge pMOSFETs with and without halo," in Proc. Int. Conf. Ultimate Integration Silicon, 2008, pp. 11-14.
9. G. Eneman, O. Sicart i Casain, E. Simoen, D. P. Brunco, B. De Jaeger, A. Satta, G. Nicholas, C. Claeys, M. Meuris, and M. M. Heyns, "Analysis of junction leakage in advanced germanium P+/n junctions," in Proc. ESSDERC, 2007, pp. 454-457.
10. A. Das, H. De, V. Misra, S. Venkatesan, S. Veeraraghavan, and M. Foisy, "Effect of halo implant on hot carrier reliability of sub-quarter micron MOSFETs," in Proc. Int. Rel. Phys. Symp., 1998, pp. 189-193.
11. K. Martens, J. Mitard, B. De Jaeger,M. Meuris, H. Maes, G. Groeseneken, F. Minucci, and F. Crupi, "Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs," in Proc. ESSDERC 2008, pp. 138-141.
12. 2 gate dielectric," in IEDM Tech. Dig., 2004, p. 558.
13. 2/Ge FETs with Si passivation," Microelectron. Eng., vol. 84, no. 9/10, pp. 2067-2070, Sep. 2007.
14. x/Si p-MOSFETs with high-k/metal gate," in VLSI Symp. Tech. Dig., 2008, pp. 56-57.
15. G. Hellings, J. Mitard, G. Eneman, B. De Jaeger, D. P. Brunco, D. Shamiryan, T. Vandeweyer, M. Meuris, M. M. Heyns, and K. De Meyer, "High performance 70 nm germanium pMOSFETs with boron LDD implants," IEEE Electron Device Lett., vol. 30, no. 1, pp. 88-90, Jan. 2009.
16. J. Mitard, B. De Jaeger, F. Leys, G. Hellings, K. Martens, G. Eneman, D. P. Brunco, R. Loo, D. Shamiryan, T. Vandeweyer, G. Winderickx, E. Vrancken, K. De Meyer, M. Caymax, L. Pantisano, M. Meuris, and M. Heyns, in IEDM Tech. Dig., San Francisco, CA, Dec. 15-17, 2008, p. 873.
17. 2 gate stack," Appl. Phys. Lett., vol. 92, no. 16, p. 163 508, Apr. 2008.
18. R. van Overstraeten and H. de Man, "Measurement of the ionization rates in diffused silicon p-n junctions," Solid State Electron., vol. 13, no. 1, pp. 583-608, Jan. 1970.