Mosfet modeling for circuit analysis and design

Mosfet Modeling For Circuit Analysis And Design

Volumn , Issue , 2007, Pages 1-420

  Galup Montoro, Carlos ^a   Schneider, Márcio Cherem ^a  

^a FEDERAL UNIVERSITY OF SANTA CATARINA   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 85115706774     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1142/6111     Document Type: Book

References (356)

1. Carver Mead and Lynn Conway, Introduction to VLSI Systems, Addison-Wesley, Reading, Mass., 1980.
2. Chih-Tang Sah, “Evolution of the MOS transistor - From conception to VLSI, " Proc. IEEE, vol. 76, no. 10, pp. 1280-1326, Oct. 1988.
3. Daniel P. Foty, MOSFET Modeling with SPICE - Principles and Practice, Prentice Hall, Upper Saddle River, NJ, 1997.
4. Henk C. de Graaff and François M. Klaassen, Compact Transistor Modelling for Circuit Design, Springer-Verlag, Wien, 1990.
5. Narain Arora, MOSFET Models for VLSI Circuit Simulation Theory and Practice, Springer-Verlag, Wien, 1993.
6. nd ed., McGraw-Hill, Boston, 1999.
7. Andrei Vladimirescu, The SPICE Book, John Wiley & Sons, New York, 1994.
8. Kenneth S. Kundert, The Designer’s Guide to SPICE & SPECTRE, Kluwer Academic Publishers, Boston, 1995.
9. Harold Shichman and David A. Hodges, “Modeling and simulation of insulated-gate field-effect transistor switching circuits, " IEEE J. Solid-State Circuits, vol. 3, no. 5, pp. 285-289, Sep. 1968.
10. John E. Meyer, “MOS models and circuit simulation, " RCA Review, vol. 32, pp. 42-63, Mar. 1971.
11. Donald E. Ward and Robert W. Dutton, “A charge-oriented model for MOS transistor capacitances, " IEEE J. Solid-State Circuits, vol. 13, no. 5, pp. 703-708, Oct. 1978.
12. William Liu, MOSFET Models for SPICE Simulation, Including BSIM3v3 and BSIM4, John Wiley & Sons, New York, 2001.
13. Bing J. Sheu, Donald L. Scharfetter, Ping-Keung Ko, and Min-Chie Jen, “BSIM:Berkeley Short-Channel IGFET Model for MOS transistors, " IEEE J. Solid-State Circuits, vol. 22, no. 4, pp. 558-566, Aug. 1987.
14. Christian C. Enz, François Krummenacher, and Eric A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications, " J. Analog Integr. Circuits Signal Process., vol. 8, pp. 83-114, July 1995.
15. Josef Watts, Colin McAndrew, Christian Enz, Carlos Galup-Montoro, Gennady Gildenblat, Chenming Hu, Ronald van Langevelde, Mitiko Miura-Mattausch, Rafael Rios, Chih-Tang Sah, “Advanced compact models for MOSFETs, " Proc. Workshop on Compact Modeling, Nanotech 2005, pp. 3-12.
16. Richard B. Adler, Arthur C. Smith, and Richard L. Longini, Introduction to Semiconductor Physics, SEEC Series, vol. 1, John Wiley & Sons, New York, 1964.
17. Chih-Tang Sah, Fundamentals of Solid-State Electronics, World Scientific, Singapore, 1991.
18. W. L. Brown, “n-type surface conductivity on p-type Ge, " Phys. Rev., vol. 91, no. 3, pp. 518-527, 1953.
19. C. G. B. Garrett and W. H. Brattain, “Physical theory of semiconductor surfaces, " Phys. Rev., vol. 99, no. 2, pp. 376-387, 1955.
20. Richard S. C. Cobbold, Theory and Applications of Field-Effect Transistors, Wiley-Interscience, New-York, 1970.
21. G. C. Dousmanis and R. C. Duncan, Jr., “Calculation on the shape and extent of space charge regions in semiconductor surfaces, " J. Appl. Phys., vol. 29, no. 12, pp. 1627-1629, Dec. 1958.
22. S. M. Sze, Physics of Semiconductor Devices, Wiley-Interscience, New York, 1969.
23. A. S. Grove, Physics and Technology of Semiconductor Devices, John Wiley & Sons, New York, 1967.
24. Dawon Kahng, “A historical perspective on the development of MOS transistors and related devices, " IEEE Trans. Electron Devices, vol. 23, no. 7, pp. 655-657, July 1976.
25. nd ed., Addison-Wesley, Reading, Mass., 1990.
26. Alexandre Ternes Behr, Márcio Cherem Schneider, Sidnei Noceti Filho, and Carlos Galup Montoro, “Harmonic distortion caused by capacitors implemented with MOSFET gates, " IEEE J. Solid-State Circuits, vol. 27, no. 10, pp. 1470-1475, Oct. 1992.
27. Yuan Taur and Tak H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, Cambridge, UK, 1998.
28. E. H. Snow, A. S. Grove, B. E. Deal, and C. T. Sah, “Ion transport phenomena in insulating films, " J. Appl. Phys., vol. 36, no. 5, pp. 1664-1673, May 1965.
29. E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, Wiley-Interscience, New York, 1982.
30. A. S. Grove, E. H. Snow, B. E. Deal, and C. T. Sah, “Simple physical model for the space-charge capacitance of metal-oxide-semiconductor structures, " J. Appl. Phys., vol. 35, no. 8, pp. 2458-2460, Aug. 1964.
31. nd ed., McGraw-Hill, Boston, 1999.
32. William Shockley, Electrons and Holes in Semiconductors, D. Van Nostrand Co., Princeton, NJ, 1950.
33. H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of metaloxide (insulator)-semiconductor transistors, " Solid-State Electron., vol. 9, no. 10, pp. 927-937, Oct. 1966.
34. Colin C. McAndrew and James J. Victory, “Accuracy of approximations in MOSFET charge models, " IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 72-81, Jan. 2002.
35. Weimin Wu, Ten-Lon Chen, Gennady Gildenblat, and Colin C. McAndrew, “Physics-based mathematical conditioning of the MOSFET surface potential equation, " IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1196-1200, July 2004.
36. Chih-Tang Sah, “A history of MOS transistor compact modeling”, Proc. Workshop on Compact Modeling, Nanotech 2005, pp. 347-390.
37. Robert H. Kingston and Siegfried F. Neustadter, “Calculation of the space charge, electric field, and free carrier concentration at the surface of a semiconductor, " J. Appl. Phys., vol. 26, no. 6, pp. 718-720, June 1955.
38. J. R Brews, “A charge-sheet model of the MOSFET, " Solid-State Electron., vol. 21, no. 2, pp.345-355, Feb. 1978.
39. F. van de Wiele, “A long-channel MOSFET model, " Solid-State Electron., vol. 22, no. 12, pp. 991-997, Dec. 1979.
40. G. Baccarani, M. Rudan, and G. Spadini, “Analytical i.g.f.e.t. model including drift and diffusion currents, " IEE J. Solid-St. and Electron Dev., vol. 2, no. 2, pp. 62-69, Mar. 1978.
41. Mary Ann Maher and Carver A. Mead, “A physical charge-controlled model for MOS transistors, " in Advanced Research in VLSI, P. Losleben (ed.), MIT Press, Cambridge, MA, 1987.
42. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “An explicit physical model for the long-channel MOS transistor including smallsignal parameters, " Solid-State Electron., vol. 38, no 11, pp. 1945-1952, Nov. 1995.
43. Jean-Michel Sallese, Matthias Bucher, François Krummenacher, and Pierre Fazan, “Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model, " Solid-State Electron., vol. 47, no. 4, pp. 677-683, Apr. 2003.
44. R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen, “Physical Background of MOS Model 11, " Nat. Lab. Unclassified Report 2003/00239, 2003. [Online]. Available: http://www.semiconductors.philips.com/Philips_Models/).
45. Gennady Gildenblat, Hailing Wang, Ten-Lon Chen, Xin Gu, and Xiaowen Cai, “SP:An advanced surface-potential-based compact MOSFET model, " IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1394-1406, Sep. 2004.
46. Carlos Galup-Montoro, Márcio Cherem Schneider, and Ana Isabela Araújo Cunha, “A current-based MOSFET model for integrated circuit design, " Chapter 2 of Low-Voltage/Low-Power Integrated Circuits and Systems, pp. 7-55, edited by Edgar Sánchez-Sinencio and Andreas G. Andreou, IEEE Press, Piscataway, NJ, 1999.
47. Christian C. Enz, François Krummenacher, and Eric A. Vittoz “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications, " J. Analog Integr. Circuits and Signal Process., vol. 8, pp. 83-114, July 1995.
48. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “Derivation of the unified charge control model and parameter extraction procedure, " Solid-State Electron., vol. 43, no. 3, pp. 481-485, Mar. 1999.
49. Young Hee Byun, Kwyro Lee, and Michael Shur, “Unified charge control model and subthreshold current in heterostructure field effect transistors, " IEEE Electron Device Lett., vol. 11, no. 1, pp. 50-53, Jan. 1990.
50. W. Shockley and W. T. Read, Jr., “Statistics of recombination of holes and electrons, " Phys. Rev., vol. 87, no. 5, pp. 835-842, Sep. 1952.
51. Roger J. Van Overstraeten, Gilbert J. Declerck, and Paul A. Muls, “Theory of the MOS transistor in weak inversion - New method to determine the number of surface states, " IEEE Trans. Electron Devices, vol. 22, no. 5, pp. 282-288, May 1975.
52. Rafael Rios and Narain D. Arora, “Determination of ultra-thin gate oxide thicknesses for CMOS structures using quantum effects, " in IEDM Tech. Dig., 1994, pp. 613-316.
53. Frank Stern, “Quantum properties of surface space-charge layers, " CRC Crit. Rev. Solid State Sci., pp. 499-514, May 1974.
54. th Int. Conf. Microelectronics (MIEL 2004), pp. 103-114.
55. M. J. van Dort, P. H. Woerlee, and A. J. Walker, “A simple model for quantization effects in heavily-doped silicon MOSFETs at inversion conditions, " Solid-State Electron., vol. 37, no. 3, pp. 411-414, Mar. 1994.
56. Rafael Rios, Narain D. Arora, Cheng-Liang Huang, Nadim Khalil, John Faricelli, and Len Gruber, “A physical compact MOSFET model, including quantum mechanical effects for statistical circuit design applications, " IEDM Tech. Dig., 1995, pp. 937-940.
57. Narain Arora, “MOSFET Models for VLSI Circuit Simulation Theory and Practice, " Springer-Verlag, Wien, 1993.
58. Dawon Kahng, “A historical perspective on the development of MOS transistors and related devices, " IEEE Trans. Electron Devices, vol. 23, no. 7, pp. 655-657, July 1976.
59. Chih-Tang Sah, “Evolution of the MOS transistor - From conception to VLSI, " Proc. IEEE, vol. 76, no. 10, pp. 1280-1326, Oct. 1988.
60. H. K. J. Ihantola and J. L. Moll, “Design theory of a surface field-effect transistor, " Solid-State Electron., vol. 7, no. 4, pp. 423-430, Apr. 1964.
61. C. T. Sah, “Characteristics of the metal-oxide-semiconductor transistor, " IEEE Trans. Electron Devices, vol. 11, no. 7, pp. 324-345, July 1964.
62. Chih-Tang Sah, “A history of MOS transistor compact modeling, " 2005 Nanotechnology Conf., presentation slides. [Online]. Available:http://www.nsti.org/Nanotech2005/WCM2005/#slides)
63. Dov Frohman-Bentchkowsky and Leslie Vadasz, “Computer-aided design and characterization of digital MOS integrated circuits, " IEEE J. Solid-State Circuits, vol. 4, no. 2, pp. 57-64, Apr. 1969.
64. Richard S. C. Cobbold, Theory and Applications of Field-Effect Transistors, Wiley-Interscience, New-York, 1970.
65. M. B. Barron, “Low level currents in insulated gate field effect transistors, " Solid-State Electron, vol. 15, no. 3, pp. 293-302, Mar. 1972.
66. R. A. Stuart and W. Eccleston, “Leakage currents of MOS devices under surfacedepletion conditions, " Electron. Lett., vol. 8, no. 9, pp. 225-227, May 1972.
67. Richard M. Swanson and James D. Meindl, “Ion-implanted complementary MOS transistors in low-voltage circuits, " IEEE J. Solid-State Circuits, vol. 7, no. 2, pp. 146-153, Apr. 1972.
68. Roger J. Van Overstraeten, G. Declerck, and George L. Broux, “Inadequacy of the classical theory of the MOS transistor operating in weak inversion, " IEEE Trans. on Electron Devices, vol. 20, no. 12, pp.1150-1153, Dec. 1973.
69. Eric Vittoz and Jean Fellrath, “CMOS analog circuits based on weak inversion operation, " IEEE J. Solid-State Circuits, vol. 12, no. 3, pp. 224-231, June 1977.
70. H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of metaloxide (insulator)-semiconductor transistors, " Solid-State Electron., vol. 9, no. 10, pp. 927-937, Oct. 1966.
71. C. Galup-Montoro, Márcio C. Schneider, and Viriato C. Pahim, “Fundamentals of next generation compact MOSFET models, " Proc. of the 18th Symp. Integr. Circ. Syst. Design, SBCCI 2005, pp. 32-37.
72. Josef Watts, Colin McAndrew, Christian Enz, Carlos Galup-Montoro, Gennady Gildenblat, Chenming Hu, Ronald van Langevelde, Mitiko Miura-Mattausch, Rafael Rios, Chih-Tang Sah, “Advanced compact models for MOSFETs, " Proc. Workshop on Compact Modeling, Nanotech 2005, pp. 3-12.
73. G. Baccarani, M. Rudan, and G. Spadini, “Analytical i.g.f.e.t. model including drift and diffusion currents, " IEE Solid-State and Electron Devices, vol. 2, no. 2, pp. 62-68, 1978.
74. J. R. Brews, “A charge sheet model for the MOSFET, " Solid-State Electronics, vol.21, no. 2, pp. 345-355, Feb. 1978.
75. F. van de Wiele, “A long-channel MOSFET model, " Solid-State Electron., vol. 22, no. 12, pp. 991-997, Dec. 1979.
76. Daniel P. Foty, MOSFET Modeling with SPICE - Principles and Practice, Prentice Hall, Upper Saddle River, NJ, 1997.
77. William Liu, MOSFET Models for SPICE Simulation, Including BSIM3v3 and BSIM4, John Wiley & Sons, New York, 2001.
78. R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen, “Physical Background of MOS Model 11, " Nat. Lab. Unclassified Report 2003/00239. [Online]. Available:http://www.semiconductors.philips.com/Philips_Models/)
79. Mary Ann Maher and Carver A. Mead, “A physical charge-controlled model for MOS transistors, " in Advanced Research in VLSI, P. Losleben (ed.), MIT Press, Cambridge, MA, 1987.
80. Mary Ann Maher, A charge-controlled model for MOS transistors, PhD Thesis, Caltech, Pasadena, CA, 1989.
81. Young Hee Byun, Kwyro Lee, and Michael Shur, “Unified charge control model and subthreshold current in heterostructure field effect transistors, " IEEE Electron Device Lett., vol. 11, no. 1, pp. 50-53, Jan. 1990.
82. S. M. Sze, Physics of Semiconductor Devices, Wiley-Interscience, New York, 1969.
83. Narain Arora, MOSFET Models for VLSI Circuit Simulation Theory and Practice, Springer-Verlag, Wien, 1993.
84. C. T. Sah and H. C. Pao, “The effects of fixed bulk charge on the characteristics of metal-oxide-semiconductor transistors, " IEEE Trans. Electron Devices, vol. 13, no. 4, pp. 393-409, April 1966.
85. W. Shockley, “A unipolar field-effect-transistor, " Proc. IRE, vol. 40, no. 11, pp. 1365-1376, Nov. 1952.
86. Eric Vittoz, “Weak inversion in analog and digital circuits”, CCCD Workshop (2003), Lund. [Online]. Available: http://www.es.lth.se/cccd/images/CCCD03-Weak%20inversion-Vittoz.pdf).
87. Gennady Gildenblat, Hailing Wang, Ten-Lon Chen, Xin Gu, and Xiaowen Cai, “SP: An advanced surface-potential-based compact MOSFET model, " IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1394-1406, Sep. 2004.
88. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “Derivation of the unified charge control model and parameter extraction procedure, " Solid-State Electron., vol. 43, no. 3, pp. 481-485, Mar. 1999.
89. Chan-Kwang Park, Chang-Yeo Lee, Kwyro Lee, Byung-Jong Moon, Young Hee Byun, and Michael Shur, “A unified current-voltage model for long channel n-MOS-FET’s, " IEEE Trans. Electron Devices, vol. 38, no. 2, pp. 399-406, Feb. 1991.
90. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “An explicit physical model for the long-channel MOS transistor including smallsignal parameters, " Solid-State Electron., vol. 38, no 11, pp. 1945-1952, Nov. 1995.
91. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “An MOS transistor model for analog circuit design, " IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, Oct. 1998.
92. Xuemei (Jane) Xi, Jin He, Mohan Dunga, Chung-Hsun Lin, Babak Heydari, Hui Wan, Mansun Chan, Ali M. Niknejad, Chenming Hu, “The development of next generation BSIM for sub-100nm mixed-signal circuit simulation, " Proc. Workshop on Compact Modeling, Nanotech 2004, pp. 70-73.
93. Christian C. Enz, François Krummenacher, and Eric A. Vittoz “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications, " J. Analog Integr. Circuits and Signal Process., vol. 8, pp. 83-114, July 1995.
94. Carlos Galup-Montoro, Márcio Cherem Schneider, and Ana Isabela Araújo Cunha, “A current-based MOSFET model for integrated circuit design, " Chapter 2 of Low-Voltage/Low-Power Integrated Circuits and Systems, pp. 7-55, edited by Edgar Sánchez-Sinencio and Andreas G. Andreou, IEEE Press, Piscataway, NJ, 1999.
95. D based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-oninsulator micropower OTA, " IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1314-1319, Sep. 1996.
96. Daniel P. Foty, MOSFET Modeling with SPICE - Principles and Practice, Prentice Hall, Upper Saddle River, NJ, 1997
97. J. R. Schrieffer, “Effective carrier mobility in surface-space charge layers, " Phys. Rev., vol. 97, no. 3, pp. 641-646, Feb. 1955.
98. S. C. Sun and James D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces, " IEEE Trans. Electron Devices, vol. 27, no. 8, pp. 1497-1508, Aug. 1980.
99. Shin-Ichi Takagi, Akira Toriumi, Masao Iwase, and Hiroyuki Tango, “On the universality of inversion layer mobility in Si MOSFET’s: Part I - Effects of substrate impurity concentration, " IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2357-2362, Dec. 1994.
100. nd ed., Cambridge University Press, Cambridge, UK, 2000.
101. nd ed., McGraw-Hill, Boston, 1999.
102. Robert F. Pierret, Advanced Semiconductor Fundamentals - Vol. VI of Modular Series on Solid State Devices, Addison-Wesley, Reading, Mass., 1987.
103. Anant G. Sabnis and James T. Clemens, “Characterization of electron mobility in the inverted <100> Si surface, " IEDM Tech. Dig., 1979, pp. 18-21.
104. Shin-Ichi Takagi, Akira Toriumi, Masao Iwase, and Hiroyuki Tango, “On the universality of inversion layer mobility in Si MOSFET’s: Part II - Effects of surface orientation, " IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2363-2368, Dec. 1994.
105. Matthias Bucher, Analytical MOS Transistor Modelling for Analog Circuit Simulation, PhD Thesis, EPFL, Lausanne, Switzerland, 1999.
106. Oscar da Costa Gouveia Filho, Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup Montoro, “Advanced compact model for short-channel MOS transistors, " Proc. CICC, 2000, pp. 209-212.
107. Steven A. Schwarz and Stephen E. Russek, “Semi-empirical equations for electron velocity in silicon: Part II - MOS inversion layer, " IEEE Trans. Electron Devices, vol. 30, no. 12, pp. 1634-1639, Dec. 1983.
108. Narain Arora, MOSFET Models for VLSI Circuit Simulation Theory and Practice, Springer-Verlag, Wien, 1990.
109. ∞ continuous smallgeometry MOSFET modeling for analog applications, " J. Analog Integr. Circ. Signal Process., vol. 13, no. 3, pp. 241-259, July 1997.
110. C. Canali, G. Majni, R. Minder, and G. Ottaviani, “Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature, " IEEE Trans. Electron Devices, vol. 22, no. 11, pp. 1045-1047, Nov. 1975.
111. R. W. Coen and R. S. Muller, “Velocity of surface carriers in inversion layers on silicon, " Solid-State Electron., vol. 23, no. 1, pp. 35-40, Jan. 1980.
112. Kwyro Lee, Michael Shur, Tor A. Fjeldly, and Trond Ytterdal, Semiconductor Device Modeling for VLSI, Prentice Hall, Englewood Cliffs, NJ, 1993.
113. Mary Ann Maher, A charge-controlled model for MOS transistors, PhD Thesis, Caltech, Pasadena, CA, 1989.
114. Mary Ann Maher and Carver A. Mead, “A physical charge-controlled model for MOS transistors, " in Advanced Research in VLSI, P. Losleben (ed.), MIT Press, Cambridge, MA, 1987.
115. M. C. Schneider, C. Galup-Montoro, O. C. Gouveia Filho, and A. I. A. Cunha., “A single-piece charge-based model for the output conductance of MOS transistors, " Proc. IEEE Int. Conf. Electron. Circ. Syst., 1998, pp. 545-548.
116. Y. A. El-Mansy and A. R. Boothroyd, " A simple two-dimensional model for IGFET operation in the saturation region, " IEEE Trans. Electron Devices, vol. 24, no. 3, pp. 254-262, Mar. 1977.
117. P. K. Ko, R. S. Muller, and C. Hu, “A unified model for hot-electron current in MOSFETs, " IEDM Tech. Dig., 1981, pp. 600-603.
118. Kenji Natori, “Ballistic metal-oxide-semiconductor field effect transistor, " J. Appl. Phys., vol. 76, no.8, pp. 4879-4890, 15 Oct. 1994.
119. Mark Lundstrom, “Elementary scattering theory of the Si MOSFET, " IEEE Electron Device Lett., vol. 18, no.7, pp. 361-363, July 1997.
120. Mark Lundstron and Zhibin Ren, “Essential physics of carrier transport in nanoscale MOSFETs, " IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 133-141, Jan. 2002.
121. Chau-Ren Ji and Chih-Tang Sah, “Two-dimensional numerical analysis of the narrow gate effect in MOSFET, " IEEE Trans. Electron Devices, vol. 30, no. 6, pp. 635-647, June 1983.
122. L. D. Yau, “A simple theory to predict the threshold voltage of short-channel IGFET’s, " Solid-State Electron., vol. 17, no. 10, pp. 1059-1063, Oct. 1974.
123. L. A. Akers and C. S. Chao, “A closed-form threshold voltage expression for a small-geometry MOSFET, " IEEE Trans. Electron Devices, vol. 29, no. 4, pp. 776-778, Apr. 1982.
124. Yuan Taur, Genda J. Hu, Robert H. Dennard, Lewis M. Terman, Chung-Yu Ting, and Karen E. Petrillo, “A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxy, " IEEE Trans. Electron Devices, vol. 32, no. 2, pp. 203-209, Feb. 1985.
125. K. N. Ratnakumar and James D. Meindl, “Short-channel MOST threshold voltage model, " IEEE J. Solid-State Circuits, vol. 17, no. 5, pp. 937-948, Oct. 1982.
126. Rafael Rios, Wei-Kai Shih, Atul Shah, Sivakumar Mudanai, Paul Packan, Tracy Sandford, and Kaizad Mistry, “A three-transistor threshold voltage model for halo processes, " IEDM Tech. Dig., 2002, pp. 113-116.
127. Narain D. Arora and Mahesh S. Sharma, “Modeling the anomalous threshold voltage behavior of submicron MOSFETs”, IEEE Electron Device Lett., vol.13, no.2, pp. 92-94, Feb. 1992.
128. Christian C. Enz, François Krummenacher and Eric A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications, " J. Analog Integr. Circuits Signal Process., vol. 8, pp. 83-114, July 1995.
129. Lex A. Akers, Moiz M. E. Beguwala, and Frank Z. Custode, “A model of a narrowwidth MOSFET including tapered oxide and doping encroachment, " IEEE Trans. Electron Devices, vol. 28, no. 12, pp. 1490-1495, Dec. 1981.
130. Ronald R. Troutman, “VLSI limitations from drain-induced barrier lowering, " IEEE Trans. Electron Devices, vol. 26, no. 4, pp. 461-469, Apr. 1979.
131. R. R. Troutman and A. G. Fortino, “Simple model for threshold voltage in a shortchannel IGFET, " IEEE Trans. Electron Devices, vol. 24, no. 10, pp. 1266-1268, Oct. 1977.
132. Savvas G. Chamberlain and Sannasi Ramanan, “Drain-induced barrier-lowering analysis in VLSI MOSFET using two-dimensional numerical simulations, " IEEE Trans. Electron Devices, vol. 33, no. 11, pp. 1745-1753, Nov. 1986.
133. C. R. Viswanathan, Bruce C. Burkey, Gerrit Lubberts, and Timothy J. Tredwell, “Threshold voltage in short-channel MOS devices, " IEEE Trans. Electron Devices, vol. 32, no. 5, pp. 932-940, May 1985.
134. Joseph M. Pimbley and James D. Meindl, “MOSFET scaling limits determined by subthreshold conduction, " IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1711-1721, Sep. 1989.
135. Zhi-Hong Liu, Chenming Hu, Jian-Hui Huang, Tung-Yi Chan, Min-Chie Jeng, Ping K. Ko, and Y. C. Cheng, “Threshold voltage for deep-submicrometer MOSFET’s, " IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 86-95, Jan. 1993.
136. Jiin-Jang Maa and Ching-Yuan Wu, “A new simplified threshold-voltage model for n-MOSFET’s with nonuniformely doped substrate and its application to MOSFET’s miniaturization, " IEEE Trans. Electron Devices, vol. 42, no. 8, pp. 1487-1494, Aug. 1995.
137. Yuan Taur and Tak H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, Cambridge, UK, 1998.
138. Yuhua Cheng, Min-Chie Jeng, Zhihong Liu, Jianhui Huang, Mansun Chan, Kai Chen, Ping Keung Ko, and Chenming Hu, “A physical and scalable I-V model in BSIM3v3 for analog/digital simulation, " IEEE Trans. Electron Devices, vol. 44, no 2, pp. 277-287, Feb. 1997.
139. Kai-Yap Toh, Ping-Keung Ko, and Robert G. Meyer, “An engineering model for short-channel MOS devices, " IEEE J. Solid-State Circuits, vol. 23, no. 4, pp. 950-958, Aug. 1988.
140. IEEE Recommended Practices #P1485 on: Test Procedures for Micro-electronic MOSFET Circuit Simulator Model Validation, 1997. [Online] Available: http://ray.eeel.nist.gov/modval
141. Yannis. P. Tsividis. and Ken Suyama, “MOSFET modeling for analog circuit CAD:problems and prospects, " IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 210-216, Mar. 1994.
142. Oscar da Costa Gouveia Filho, Um modelo compacto do transistor MOS para simulação de circuitos, PhD Thesis, Federal University of Santa Catarina, Florianopolis, Brazil, 1999 (in Portuguese).
143. SMASH Users Manual, Dolphin Integration, Meylan, France, 1995.
144. Soo-Young Oh, Donald E. Ward, and Robert W. Dutton, “Transient analysis of MOS transistors, " IEEE Trans. Electron Devices, vol. 27, no. 8, pp. 1571-1578, Aug. 1980.
145. John E. Meyer, “MOS models and circuit simulation, " RCA Review, vol. 32, pp. 42-63, Mar. 1971.
146. Richard B. Adler, Arthur C. Smith, and Richard L. Longini, Introduction to Semiconductor Physics, SEEC Series, vol. 1, John Wiley & Sons, New York, 1964.
147. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “An explicit physical model for the long-channel MOS transistor including smallsignal parameters, " Solid-State Electron., vol. 38, no 11, pp. 1945-1952, Nov. 1995.
148. J. J. Paulos and D. A. Antoniadis, “Limitations of quasi-static capacitance models for the MOS transistor, " IEEE Electron Device Lett., vol. 4, no. 7, pp. 221-224, July 1983.
149. nd ed., McGraw-Hill, Boston, 1999.
150. Claudio Turchetti, Guido Masetti and Yannis Tsividis, “On the small signal behavior of the MOS transistor in quasi-static operation, " Solid-State Electron., vol. 26, no. 10, pp. 941-949, Oct. 1983.
151. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “An MOS transistor model for analog circuit design, " IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, Oct. 1998.
152. Carlos Galup-Montoro, Márcio Cherem Schneider, and Ana Isabela Araújo. Cunha, “A current-based MOSFET model for integrated circuit design, " Chapter 2 of Low-Voltage/Low-Power Integrated Circuits and Systems, pp. 7-55, edited by Edgar Sánchez-Sinencio and Andreas G. Andreou, IEEE Press, Piscataway, NJ, 1999.
153. Kenneth S. Kundert, The Designer’s Guide to SPICE & SPECTRE, Kluwer Academic Publishers, Boston, 1995
154. Oscar da Costa Gouveia Filho, Um modelo compacto do transistor MOS para simulação de circuitos, PhD Thesis, Federal University of Santa Catarina, Florianopolis, Brazil, 1999 (in Portuguese).
155. ACM model (1997), [Online]. Available: http://eel.ufsc.br/lci/acm/index.html
156. Oscar da Costa Gouveia Filho, Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup Montoro, “Advanced compact model for short-channel MOS transistors, " Proc. IEEE CICC 2000, pp. 209-212.
157. International Technology Roadmap for Semiconductors (2004 update). [Online]. Available: http://public.itrs.net/
158. Bin Yu, Haihong Wang, Amol Joshi, Qi Xiang, Effiong Ibok, and Ming-Ren Lin, "15 nm gate length planar CMOS transistor, " IEDM Tech. Dig., 2001, pp. 937-939.
159. Jyn-Bang Shyu, Gabor C. Temes, and François Krummenacher, “Random error effects in matched MOS capacitors and current sources, " IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 948-955, Dec. 1984.
160. nd ed., Kluwer Academic Publishers, Dordrecht, The Netherlands, 2000.
161. Marcel J. M. Pelgrom, Aad C. J. Duinmaijer, and Anton P. G. Welbers, “Matching properties of MOS transistors, " IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440, Oct. 1989.
162. Francesco Forti and Michael E. Wright, “Measurements of MOS current mismatch in the weak inversion region, " IEEE J. Solid-State Circuits, vol. 29, no. 2, pp. 138-142, Feb. 1994.
163. Marcel J. M. Pelgrom, Hans P. Tuinhout, and Maarten Vertregt, “Transistor matching in analog CMOS applications, " IEDM Tech. Dig., 1998, pp. 915-918.
164. Ron Wilson, “The dirty little secret: Engineers at design forum vexed by rise in process variations at the die level, " EE Times, Mar. 25, 2002, p. 1.
165. Alan Hastings, The Art of Analog Layout, Prentice Hall, Upper Saddle River, NJ, 2001.
166. Robert W. Keyes, “Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics, " IEEE J. Solid-State Circuits, vol. 10, no. 4, pp. 245-247, Aug. 1975.
167. Kadaba R. Lakshmikumar, Robert A. Hadaway, and Miles A. Copeland, “Characterization and modeling of mismatch in MOS transistors for precision analog design, " IEEE J. Solid-State Circuits, vol. 21, no. 6, pp. 1057-1066, Dec. 1986.
168. rd IEEE MWSCAS, 2000, pp. 1324-1328.
169. Hongning Yang, Véronique Macary, John L. Huber, Won-Gi Min, Bob Baird, and Jiangkai Zuo, “Current mismatch due to local dopant fluctuations in MOSFET channel, " IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2248-2254, Nov. 2003.
170. Alfredo Arnaud and Carlos Galup-Montoro, “A compact model for flicker noise in MOS transistors for analog circuit design, " IEEE Trans. Electron Devices, vol. 50, no. 8, pp. 1815-1818, Aug. 2003.
171. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “An MOS transistor model for analog circuit design, " IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, Oct. 1998.
172. nd ed., McGraw-Hill, Boston, 1999.
173. Carlos Galup-Montoro, Márcio Cherem Schneider, and Ana Isabela Araújo Cunha, “A current-based MOSFET model for integrated circuit design, " Chapter 2 of Low-Voltage/Low-Power Integrated Circuits and Systems, pp. 7-55, edited by Edgar Sánchez-Sinencio and Andreas G. Andreou, IEEE Press, Piscataway, NJ, 1999.
174. Tomohisa Mizuno, Jun-ichi Okamura, and Akira Toriumi, “Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET’s, " IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 2216-2221, Nov. 1994.
175. Kwok K. Hung, Ping K. Ko, Chenming Hu, and Yiu C. Cheng, “A physics-based MOSFET noise model for circuit simulators, " IEEE Trans. Electron Devices, vol. 37, no. 5, pp. 1323-1333, May 1990.
176. G. Reimbold, “Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion - influence of interface states, " IEEE Trans. Electron Devices, vol. 31, no. 9, pp. 1190-1198, Sep. 1984.
177. F. Berz, “Theory of low frequency noise in Si MOST’s, " Solid-State Electron., vol. 13, no. 5, pp. 631-647, May 1970.
178. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “Derivation of the unified charge control model and parameter extraction procedure, " Solid-State Electron., vol. 43, no. 3, pp. 481-485, Mar. 1999.
179. P. A. Stolk and D. B. M. Klaassen, “The effect of statistical dopant fluctuations on MOS device performance, " IEDM Tech. Dig., 1996, pp. 627-630.
180. Kiyoshi Takeuchi, Toru Tatsumi, and Akio Furukawa, “Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation, " IEDM Tech. Dig., 1997, pp. 841-844.
181. Carlos Galup-Montoro, Márcio C. Schneider, Hamilton Klimach, and Alfredo Arnaud, “A compact model of MOSFET mismatch for circuit design, " IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1649-1657, Aug. 2005.
182. Hamilton Klimach, Carlos Galup-Montoro, Márcio C. Schneider and Alfredo Arnaud, “MOSFET mismatch modeling: A new approach, " IEEE Design and Test of Computers, vol. 23, no. 1, pp. 20-29, Jan.-Feb. 2006.
183. Marcel J. M. Pelgrom, “Low-power CMOS data conversion, " Chap. 14 in Low-Voltage/Low-Power Integrated Circuits and Systems, pp. 432-484, edited by Edgar Sánchez-Sinencio and Andreas G. Andreou, IEEE Press, Piscataway, NJ, 1999.
184. M. Steyaert, J. Bastos, R. Roovers, P. Kinget, W. Sansen, B. Graindourze, A. Pergoot, E. Janssens., “Threshold voltage mismatch in short-channel MOS transistors, " Electron. Lett., vol. 30, no. 18, pp. 1546-1548, Sep. 1994.
185. José Pineda de Gyvez and Hans P. Tuinhout, “Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits, " IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 157-168, Jan. 2004.
186. Ming-Jer Chen, Jih-Shin Ho, and Tzuen-Hsi Huang, “Dependence of current match on back-gate bias in weakly inverted MOS transistor and its modeling, " IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 259-262, Feb. 1996.
187. Jeroen A. Croon, Maarten Rosmeulen, Stefaan Decoutere, Willy Sansen, and Herman E. Maes, “An easy-to-use mismatch model for the MOS transistor, " IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1056-1064, Aug. 2002.
188. Shyh-Chyi Wong, Kuo-Hua Pan, and Dye-Jyun Ma, “A CMOS mismatch model and scaling effects, " IEEE Electron Device Lett., vol. 18, no. 6, pp. 261-263, June 1997.
189. R. Difrenza, P. Linares, E. Granger, H. Brut, G. Ghibaudo, “Effect of substrate voltage and oxide thickness on NMOSFET matching characteristics for a 0.18 µm CMOS technology, " Proc. IEEE ICMTS, 2001, pp. 7-10.
190. C. T. Sah, “Theory and experiments on the 1/f surface noise of MOS insulated-gate field-effect transistors, " IEEE Trans. Electron Devices, vol. 11, no. 11, p. 534, Nov. 1964.
191. A. G. Jordan and N. A. Jordan, “Theory of noise in metal oxide semiconductors devices, " IEEE Trans. Electron Devices, vol. 12, no. 3, pp. 148-156, Mar. 1965.
192. H. K. J. Ihantola and J. L. Moll, “Design theory of a surface field-effect transistor, " Solid-State Electron., vol. 7, no. 4, pp. 423-430, Apr. 1964.
193. C. T. Sah, “Characteristics of the metal-oxide-semiconductor transistor, " IEEE Trans. Electron Devices, vol. 11, no. 7, pp. 324-345, July 1964.
194. A. van der Ziel, “Theory of noise in field effect transistors, " IEEE Trans. Electron Devices, vol. 9, no. 11, p. 507, Nov. 1962.
195. C. T. Sah, “Theory of low-frequency generation noise in junction-gate field effect transistors, " Proc. IEEE, vol. 52, no. 7, pp. 795-814, July 1964.
196. Albert Einstein, Investigations on the Theory of the Brownian Movement, Dover Publications, New York, 1956.
197. H. Nyquist, “Thermal agitation of electric charge in conductors, " Phys. Rev., vol. 32, no. 1, pp. 110-113, July 1928.
198. J. R. Pierce, “Physical sources of noise, " Proc. IRE, vol. 44, pp. 601-608, May 1956.
199. J. B. Johnson, “Thermal agitation of electricity in conductors, " Phys. Rev., vol. 32, no. 1, pp. 97-109, July 1928.
200. rd ed., John Wiley & Sons, New York, 1993.
201. J. R. Ragazzini and S. S. L. Chang, “Noise and random processes, " Proc. IRE, vol. 50, pp. 1146-1151, May 1962.
202. Aldert van der Ziel, Noise in Solid State Devices and Circuits, Wiley-Interscience, New York, 1986.
203. Alfredo Arnaud Maceira, Very Large Time Constant Gm-C Filters, Ph. D. Thesis, Universidad de la Republica, Uruguay, 2004. [Online]. Available: http://eel.ufsc.br/~lci/work_doct.html
204. W. Shockley, John A. Copeland, and R. P. James, “The impedance field method of noise calculation in active semiconductor devices, " pp. 537-563 in Quantum Theory of Atoms, Molecules and the Solid-State, Academic Press, New York, 1966.
205. Jung-Suk Goo, High-Frequency Noise in CMOS Low Noise Amplifiers, PhD Thesis, Stanford, CA, 2001. [Online]. Available: http://www-tcad.stanford.edu/tcad/pubs/theses/goo.pdf).
206. Richard S. C. Cobbold, Theory and Applications of Field-Effect Transistors, Wiley-Interscience, New York, 1970.
207. Alfredo Arnaud and Carlos Galup-Montoro, “A compact model for flicker noise in MOS transistors for analog circuit design, " IEEE Trans. Electron Devices, vol. 50, no. 8, pp. 1815-1818, Aug. 2003.
208. F. N. Hooge, "1/f noise sources, " IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 1926-1935, Nov. 1994.
209. C. T. Sah, S. Y. Wu, and F. H. Hielscher, “The effects of fixed bulk charge on the thermal noise in metal-oxide-semiconductor transistors, " IEEE Trans. Electron Devices, vol. 13, no. 4, pp. 410-414, Apr. 1966.
210. S. Christensson, I. Lundstrom, and C. Svensson, “Low frequency noise in MOS transistors-I Theory, " Solid-State Electron., vol. 11, no. 9, pp.797-812, Sep. 1968.
211. F. Berz, “Theory of low frequency noise in Si MOSTs, " Solid-State Electron., vol. 13, no. 5, pp. 631-647, May 1970.
212. Kwok K. Hung, Ping K. Ko, Chenming Hu, and Yiu C. Cheng., “A physics-based MOSFET noise model for circuit simulators, " IEEE Trans. Electron Devices, vol. 37, no. 5, pp. 1323-1333, May 1990.
213. G. Reimbold, “Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion-influence of interface states, " IEEE Trans. Electron Devices, vol. 31, no. 9, pp. 1190-1198, Sep. 1984.
214. Carlos Galup-Montoro, Márcio C. Schneider, and Itamar J. B. Loss, “Series-parallel association of FETs for high gain and high frequency applications, " IEEE J. Solid-State Circuits, vol. 29, no. 9, pp. 1094-1101, Sep. 1994.
215. Christian C. Enz and Eric A. Vittoz, “CMOS low-power analog circuit design, " pp. 79-133, in Emerging Technologies, Ralph Cavin and Wentai Liu (eds.), IEEE Press, Piscataway, NJ, 1996.
216. Alfredo Arnaud and Carlos Galup-Montoro, “Consistent noise models for analysis and design of CMOS circuits, " IEEE Trans. Circuits Systems I, vol. 51, no. 10, pp. 1909-1915, Oct. 2004.
217. Kwangseok Han, Hyungcheol Shin, and Kwyro Lee, “Analytical drain thermal noise current model valid for deep submicron MOSFETs, " IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 261-269, Feb. 2004.
218. Carlo Jacobini and Lino Reggiani, “Bulk hot-electron properties of cubic semiconductors, " Advances in Physics, vol. 28, no. 4, pp. 493-553, 1979.
219. nd ed., Cambridge University Press, Cambridge, UK, 2000.
220. nd ed., McGraw-Hill, Boston, 1999
221. William Liu, MOSFET Models for SPICE Simulation including BSIM3v3 and BSIM4, John Wiley & Sons, New York, 2001.
222. Behnam Aghdaie and Bing Sheu, “Overcoming limitations of lumped MOS models, " IEEE Circuits Devices Mag., vol. 16, no. 2, pp. 19-26, Mar. 2000.
223. R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen, Physical background of MOS model 11, Nat. Lab. Unclassified Report 2003/00239. [Online]. Available: http://www.semiconductors.philips.com/Philips_Models/
224. Mehran Bagheri and Yannis Tsividis, “A small signal dc-to-high-frequency nonquasistatic model for the four-terminal MOSFET valid in all regions of operation, " IEEE Trans. Electron Devices, vol. 32, no. 11, pp. 2383-2391, Nov. 1985.
225. Mehran Bagheri, Solutions manual to accompany Tsividis Operation and Modeling of the MOS Transistor, McGraw-Hill, New York, 1987.
226. A.-S. Porret and C. C. Enz, “Non-quasi-static (NQS) thermal noise modelling of the MOS transistor, " IEE Proc.-Circuits Devices Syst., vol. 151, no. 2, pp. 155-166, Apr. 2004.
227. Alain-Serge Porret, Design of a Low-Power and Low-Voltage UHF Transceiver Integrated in a CMOS Process, PhD Thesis, EPFL, Lausanne, Switzerland, 2002.
228. Narain Arora, MOSFET Models for VLSI Circuit Simulation Theory and Practice, Springer-Verlag, Wien, 1993.
229. Paolo Mancini, Claudio Turchetti, and Guido Masetti, “A non-quasi-static analysis of the transient behavior of the long channel MOST valid in all regions of operation, " IEEE Trans. Electron Devices, vol. 34, no. 2, pp. 325-334, Feb. 1987.
230. Soo-Young Oh, Donald E. Ward, and Robert W. Dutton, “Transient analysis of MOS transistors, " IEEE Trans. Electron Devices, vol. 27, no. 8, pp. 1571-1578, Aug. 1980.
231. D. H. Treleaven and F. N. Trofimenkoff, “MOS FET equivalent circuit at pinch-off, " Proc. IEEE, vol. 54, no. 9, pp. 1223-1224, Sep. 1966.
232. J. M. Sallese and A.-S. Porret, “A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation, " Solid-State Electron., vol. 44, no. 6, pp. 887-894, June 2000.
233. J. A. van Nielen, “A simple and accurate approximation to the high-frequency characteristics of insulated-gate field-effect transistors, " Solid-State Electron., vol. 12, no. 10, pp. 826-829, Oct. 1969.
234. Ana Isabela Araújo Cunha, Um Modelo do Transistor MOS para Projeto de Circuitos Integrados, PhD Thesis, Universidade Federal de Santa Catarina, Florianópolis, Brazil, 1996 (in Portuguese). [Online]. Available: http://eel.ufsc.br/~lci/publications.html
235. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “An MOS transistor model for analog circuit design, " IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, Oct. 1998.
236. Carlos Galup-Montoro, Márcio Cherem Schneider, and Ana Isabela Araújo Cunha, “A current-based MOSFET model for integrated circuit design, " Chapter 2 in Low-Voltage/Low-Power Integrated Circuits and Systems, pp. 7-55, edited by Edgar Sánchez-Sinencio and Andreas G. Andreou, IEEE Press, Piscataway, NJ, 1999.
237. A. J. Scholten, L. F. Tiemeijer, P. W. H. de Vreede, and D. B. M. Klaassen, “A large signal non-quasi-static MOS model for RF circuit simulation, " IEDM Tech. Dig., 1999, pp. 163-166.
238. Andries J. Scholten, Luuk F. Tiemeijer, Ronald van Langevelde, Ramon J. Havens, Adrie T. A. Zegers-van Duijnhoven, and Vincent C. Venezia, “Noise modeling for RF CMOS circuit simulation, " IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 618-632, Mar. 2003.
239. A. van der Ziel, “Gate noise in field effect transistors at moderately high frequencies, " Proc. IEEE, vol. 51, no. 3, pp. 461-467, Mar. 1963.
240. Masakazu Shoji, “Analysis of high-frequency thermal noise of enhancement mode MOS field-effect transistors, " IEEE Trans. Electron Devices, vol. 13, no. 6, pp. 520-524, June 1966.
241. Aldert van der Ziel, Noise in Solid State Devices and Circuits, Wiley-Interscience, New York, 1986.
242. Aldert van der Ziel, “Noise in solid-state devices and lasers, " Proc. IEEE, vol. 58, no. 8, pp. 1178-1206, Aug. 1970.
243. 2, " J. Appl. Phys., vol. 40, no. 1, pp. 278-283, Jan. 1969.
244. Michael Shur, Introduction to Electronic Devices, John Wiley & Sons, New York, 1996.
245. Andreas Gehring and Siegfried Selberherr, “Gate currents in small MOSFETs, " presentation at the EDS South-Brazil Chapter Meeting, Campinas, Brazil, 2004.
246. R. Clerc, B. de Salvo, G. Ghibaudo, G. Reimbold, and G. Pananakakis., “Electrical characterization and modeling of MOS structures with an ultra-thin oxide, " Solid-State Electron., vol. 46, no. 3, pp. 407-416, Mar. 2002.
247. Farhan Rana, Sandip Tiwari, and D. A. Buchanan, “Self-consistent modeling of accumulation layers and tunneling currents through very thin oxides, " Appl. Phys. Lett., vol. 69, no. 8, pp. 1104-1106, 1996.
248. Leonard F. Register, Elyse Rosenbaum, and Kevin Yang, “Analytic model for direct tunneling current in polycrystalline silicon-gate metal-oxide-semiconductor devices, " Appl. Phys. Lett., vol. 74, no. 3, pp. 457-459, 1999.
249. 2 breakdown model for very low voltage lifetime extrapolation, " IEEE Trans. Electron Devices, vol. 41, no. 5, pp. 761-767, May 1994.
250. K. M. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S. K. H. Fung, J. X. An, B. Yu, and C. Hu, “BSIM4 gate leakage model including source-drain partition, " IEDM Tech. Dig., 2000, pp. 815-818.
251. R. Clerc, P. O’Sullivan, K. G. McCarty, G. Ghibaudo, G. Pananakakis, A. Mathewson, “A physical compact model for direct tunneling from NMOS inversion layers, " Solid-State Electron., vol. 45, no. 10, pp. 1705-1716, Oct. 2001.
252. Z. A. Weinberg, “On tunneling in metal-oxide-silicon structures, " J. Appl. Phys., vol. 53, no. 7, pp. 5052-5056, July 1982.
253. Frank Stern, “Quantum properties of surface space-charge layers, " CRC Crit. Rev. Solid State Sci., pp. 499-514, 1974.
254. 2, " Solid-State Electron., vol. 20, no. 1, pp. 11-18, Jan. 1977.
255. R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen, “Physical Background of MOS Model 11, " Nat. Lab. Unclassified Report 2003/00239. [Online]. Available: http://www.semiconductors.philips.com/Philips_Models/
256. R. Clerc, A. Spinelli, G. Ghibaudo, and G. Pananakakis, “Theory of direct tunneling current in metal-oxide-semiconductor structures, " J. Appl. Phys., vol. 91, no. 3, pp. 1400-1409, Feb. 2002.
257. Jin Cai and Chih-Tang Sah, “Gate tunneling currents in ultrathin oxide metal-oxidesilicon transistors, " J. Appl. Phys., vol. 89, no.4, pp. 2272-2285, Feb. 2001.
258. Wei-Kai Shih, Rafael Rios, Paul Packan, Kaizad Mistry, Tracy Abbott, “A general partition scheme for gate leakage current suitable for MOSFET compact models, " IEDM Tech. Dig., 2001, pp. 293-296.
259. R. van Langevelde, A. J. Scholten, R. Duffy, F. N. Cubaynes, M. J. Knitel, and D. B. M. Klaassen, “Gate current: modeling, ΔL extraction and impact on RF performance, " IEDM Tech. Dig., 2001, pp. 289-292.
260. J. Chen, T. Y. Chan, I. C. Chen, P. K. Ko, and Chenming Hu, “Subbreakdown drain leakage current in MOSFET, " IEEE Electron Device Lett., vol. 8, no. 11, pp. 515-517, Nov. 1987.
261. Tetsuo Endoh, Riichiroh Shirota, Masaki Momodomi, and Fujio Masuoka, “An accurate model of subbreakdown due to band-to-band tunneling and some applications, " IEEE Trans. Electron Devices, vol. 37, no. 1, pp. 290-296, Jan. 1990.
262. Ja-Hao Chen, Shyh-Chyi Wong, and Yeong-Her Wang, “An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET, " IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1400-1405, July 2001.
263. S. M. Sze, Physics of Semiconductor Devices, Wiley-Interscience, New York, 1969.
264. C. A. Lee, R. A. Logan, R. L. Batdorf, J. J. Kleimack, and W. Wiegmann, “Ionization rates of holes and electrons in silicon, " Phys. Rev., vol. 134, no. 3A, pp. A761-773, 1964.
265. Y. A. El-Mansy and D. M. Caughey, “Modeling weak avalanche multiplication currents in IGFETS and SOS transistors for CAD, " IEDM Tech. Dig., 1975, pp. 31-34.
266. Ronald R. Troutman, “Low-level avalanche multiplication in IGFET’s, " IEEE Trans. Electron Devices, vol. 23, no. 4, pp. 419-425, Apr. 1976.
267. J. W. Slotboom, G. Streutker, G. J. T. Davids, and P. B. Hartog, “Surface impact ionization in silicon devices, " IEDM Tech. Dig., 1987, pp. 494-497.
268. Narain Arora, MOSFET Models for VLSI Circuit Simulation Theory and Practice, Springer-Verlag, Wien, 1993.
269. Fu-Chieh Hsu, Ping-Keung Ko, Simon Tam, Chenming Hu, and Richard S. Muller, “An analytical breakdown model for short-channel MOSFET’s, " IEEE Trans. Electron Devices, vol. 29, no. 11, pp. 1735-1740, Nov. 1982.
270. Chang-Hoon Choi, Ki-Young Nam, Zhiping Yu, and Robert W. Dutton, “Impact of gate direct tunneling current on circuit performance: a simulation study, " IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2823-2829, Dec. 2001.
271. International Technology Roadmap for Semiconductors (2004 update). [Online]. Available: http://public.itrs.net/
272. H.-S. P. Wong, “Beyond the conventional transistor, " IBM J. Res. Dev., vol. 46, no. 2/3, pp. 133-168, Mar./May 2002.
273. Yuan Taur, Douglas A. Buchanan, Wei Chen, David J. Frank, Khalid E. Ismail, Shih-Hsien Lo, George A. Sai-Halasz, Raman G. Viswanathan, Hsing-Jen C. Wann, Shalom J. Wind, Hon-Sum Wong, “CMOS scaling into the nanometer regime, " Proc. IEEE, vol. 85, no. 4, pp. 486-504, Apr. 1997.
274. st century: 0.1 µm and beyond, " IBM J. Res. Dev., vol. 39, no. 1/2, pp. 245-260, Jan./Mar. 1995.
275. Rafael Rios, Wei-Kai Shih, Atul Shah, Sivakumar Mudanai, Paul Packan, Tracy Sandford, and Kaizard Mistry, “A three-transistor threshold voltage model for halo processes, " IEDM Tech. Dig., 2002, pp. 113-116.
276. Takashi Hori, “A 0.1 µm CMOS technology with Tilt-Implanted Punchthrough Stopper (TIPS), " IEDM Tech. Dig., 1994, pp. 75-78.
277. Yuan Taur and Edward J. Nowak, “CMOS devices below 0.1µm: How high will performance go?, " IEDM Tech. Dig., 1997, pp. 215-218.
278. Hioraki Ueno, Daisuke Kitamaru, Keiichi Morikawa, Masayasu Tanaka, Mitiko Miura-Mattausch, Hans Juergen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, and Noriaki Nakayama, “Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation, " IEEE Trans. Electron Devices, vol. 49, no. 10, pp. 1783-1789, Oct. 2002.
279. Y. Okumura, M. Shirahata, T. Okudaira, A. Hachisuka, H. Arima, T. Matsukawa, and N. Tsubouchi, “A novel source-to-drain nonuniformly doped channel (NUDC) MOSFET for high-current drivability and threshold voltage controllability, " IEDM Tech. Dig., 1990, pp. 391-394.
280. G. G. Shahidi, “SOI technology for the GHz era, " IBM J. Res. Dev., vol. 46, no. 2/3, pp. 121-131, Mar./May 2002.
281. K. Hashimoto, T. I. Kamins, K. M. Cham, and S. Y. Chiang, “Characteristics of sub-micron CMOS transistors in implanted-buried-oxide SOI films, " IEDM Tech. Dig., 1985, pp. 672-675.
282. Yuan Taur and Tak H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, Cambridge, UK, 1998.
283. Bernard M. Tenbroek, Michael S. L. Lee, William Redman-White, R. John T. Bunyan, and Michael J. Uren, “Impact of self-heating and thermal coupling on analog circuits in SOI CMOS, " IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 1037-1046, July 1998.
284. Lisa T. Su, Jarvis B. Jacobs, James E. Chung, and Dimitri A. Antoniadis, “Deepsubmicrometer channel design in silicon-on-insulator (SOI) MOSFET’s, " IEEE Electron Device Lett., vol. 15, no. 9, pp. 366-369, Sep. 1994.
285. Hyung-Kyu Lim and Jerry G. Fossum, “Current-voltage characteristics of thin-film SOI MOSFET’s in strong inversion, " IEEE Trans. Electron Devices, vol. 31, no. 4, pp. 401-408, Apr. 1984.
286. Hyung-Kyu Lim and Jerry G. Fossum, “A charge-based large-signal model for thinfilm SOI MOSFET’s, " IEEE Trans. Electron Devices, vol. 32, no. 2, pp. 446-457, Feb. 1985.
287. Adelmo Ortiz-Conde, Francisco J. García Sánchez, Pierre E. Schmidt, and Augusto Sa-Neto, “The nonequilibrium inversion layer charge of the thin-film SOI MOSFET, " IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1651-1656, Sep. 1989.
288. C. Mallikarjun and K. N. Bhat, “Numerical and charge sheet models for thin-film SOI MOSFET’s, " IEEE Trans. Electron Devices, vol. 37, no. 9, pp. 2039-2051, Sep. 1990.
289. ∞-continuous fully-depleted SOI MOSFET model for analog applications, " IEEE Trans. Electron Devices, vol. 43, no. 4, pp. 568-575, Apr. 1996.
290. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “An MOS transistor model for analog circuit design, " IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, Oct. 1998.
291. A. Ortiz-Conde, F. J. García Sánchez, P. E. Schmidt and A. Sa-Neto, “The foundation of a charge-sheet model for the thin-film MOSFET, " Solid-State Electron., vol. 31, no. 10, pp. 1497-1500, Oct. 1988.
292. Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka, “Impact of surrounding gate transistor (SGT) for ultra-high-density LSI’s, " IEEE Trans. Electron Devices, vol. 38, no. 3, pp. 573-578, Mar. 1991.
293. Shigeyoshi Watanabe, Kenji Tsuchida, Daisaburo Takashima, Yukihito Oowaki, Akihiro Nitayama, Katsuhiko Hieda, Hirishi Takato, Kazumasa Sunouchi, Fumio Horiguchi, Kazunori Ohuchi, Fujio Masuoka, and Hisashi Hara, “A novel circuit technology with surrounding gate transistors (SGT’s) for ultra- high density DRAM’s, " IEEE. J. Solid-State Circuits, vol. 30, no. 9, pp. 960-971, Sep. 1995.
294. Christopher P. Auth and James D. Plummer, “Scaling theory for cylindrical fullydepleted surrounding- gate MOSFET’s, " IEEE Electron Device Lett., vol. 18, no. 2, pp. 74-76, Feb. 1997.
295. Yijian Chen and Jianfeng. Luo, “A comparative study of double-gate and surrounding-gate MOSFETs in strong inversion and accumulation using an analytical model, " in Proc. Int. Conf. on Modeling and Simulation of Microsystems, 2001, pp. 546-549.
296. Benjamin Iñíguez, David Jiménez, Jaume Roig, Hamdy A. Hamid, Lluís F. Marsal, Josep Pallarès, “Explicit continuous model for long-channel undoped surrounding gate MOSFETs, " IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1868-1873, Aug. 2005.
297. P. L. Chambré, “On the solution of the Poisson-Boltzmann equation with application to the theory of thermal explosions, " J. Chem. Phys., Vol. 20, no. 11, pp. 1795-1797, Nov. 1952.
298. J. Brini, M. Benachir, G. Ghibaudo, F. Balestra, “Threshold voltage and subthreshold slope of the volume-inversion MOS transistor, " IEE Proc.-G, vol. 138, no. 1, pp. 133-136, Feb. 1991.
299. D. Jiménez, B. Iñíguez, J. Suñé, L. F. Marsal, J. Pallarès, J. Roig, and D. Flores, “Continuous analytic I-V model for surrounding-gate MOSFETs, " IEEE Electron Device Lett., vol. 25, no. 8, pp. 571-573, Aug. 2004.
300. Jong-Tae Park and Jean-Pierre Colinge, “Multiple-gate SOI MOSFETs: device design guidelines, " IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2222-2229, Dec. 2002.
301. Qiang Chen, Evans M. Harrell II, and James D. Meindl, “A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs, " IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1631-1637, July 2003.
302. Yuan Taur, “An analytical solution to a double-gate MOSFET with undoped body, " IEEE Electron Device Lett., vol. 21, no. 5, pp. 245-247, May 2000.
303. Yuan Taur, Xiaoping Liang, Wei Wang, and Huaxin Lu, “A continuous analytic drain-current model for DG MOSFETs, " IEEE Electron Device Lett., vol. 25, no. 2, pp. 107-109, Feb. 2004.
304. Xiaoping Liang and Yuan Taur, “A 2-D analytical solution for SCEs in DG MOSFETs, " IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1385-1391, Sep. 2004.
305. B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, “High performance fully-depleted tri-gate CMOS transistors, " IEEE Electron Device Lett., vol. 24, no. 4, pp. 263-265, Apr. 2003
306. B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios and R. Chau, “Tri-gate fully-depleted CMOS transistors:fabrication, design and layout, " Symp. VLSI Tech., 2003, pp. 133-134.
307. Robert Chau, Boyan Boyanov, Brian Doyle, Mark Doczy, Suman Datta, Scott Hareland, Ben Jin, Jack Kavalieros, and Matthew Metz, “Silicon nano-transistors for logic applications, " Physica E, vol. 19, no. 1-2, pp. 1-5, July 2003.
308. Brian Doyle, Reza Arghavani, Doug Barlage, Suman Datta, Mark Doczy, Jack Kavalieros, Anand Murthy, and Robert Chau, “Transistor elements for 30nm physical gate lengths and beyond, " Intel Tech. J., vol. 6, no.2, pp. 42-54, May 2002.
309. Xuejue Huang, Wen-Chin Lee, Charles Kuo, Digh Hisamoto, Leland Chang, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Yang-Kyu Choi, Kazuya Asano, Vivek Subramanian, Tsu-Jae King, Jeffrey Bokor, and Chenming Hu, “Sub 50-nm FinFET: PMOS, " IEDM Tech. Dig., 1999, p. 67-70.
310. Colin C. McAndrew and Paul A. Layman, “MOSFET effective channel length, threshold voltage, and series resistance determination by robust optimization, " IEEE Trans. Electron Devices, vol. 39, no. 10, pp. 2298-2311, Oct. 1992.
311. Narain Arora, MOSFET Models for VLSI Circuit Simulation Theory and Practice, Springer-Verlag, Wien, 1993.
312. nd ed., McGraw-Hill, Boston, 1999.
313. A. Ortiz-Conde, F. J. García Sánchez, J. J. Liou, A. Cerdeira, M. Estrada, Y. Yue, “A review of recent MOSFET threshold voltage extraction methods, " Microelectronics Reliability, vol. 42, no. 4-5, pp. 583-596, Apr-May 2002.
314. X. Zhou, K. Y. Lim, and D. Lim, “A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling, " IEEE Trans. Electron Devices, vol.46, no. 4, pp. 807-809, Apr. 1999.
315. Morikazu Tsuno, Masato Suga, Masayasu Tanaka, Kentaro Shibahara, Mitiko Miura-Mattausch, and Masataka Hirose, “Physically-based threshold voltage determination for MOSFET’s of all gate lengths, " IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1429-1434, July 1999.
316. A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro, C. D. C. Caetano, and M. B. Machado, “Unambiguous extraction of threshold voltage based on the transconductance-to-current ratio, " Proc. Workshop on Compact Modeling, Nanotech 2005, pp. 139-142.
317. A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro, C. D. C. Caetano, and M. B. Machado, “Extraction of MOSFET effective channel length and width based on the transconductance-to-current ratio, " Proc. Workshop on Compact Modeling, Nanotech 2005, pp. 135-138.
318. Bin Yu, Clement H. J. Wann, Edward D. Nowak, Kenji Noda, and Chenming Hu, “Short-channel effect improved by lateral channel-engineering in deepsubmicronmeter MOSFET’s, " IEEE Trans. Electron Devices, vol. 44, no. 4, pp. 627-634, Apr. 1997.
319. Matthias Bucher, Christophe Lallement and Christian C. Enz, “An efficient parameter extraction methodology for the EKV MOST model, " Proc. IEEE ICMTS, 1996, pp. 145-150.
320. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “Derivation of the unified charge control model and parameter extraction procedure, " Solid-State Electron., vol. 43, no. 3, pp. 481-485, Mar. 1999.
321. Anant G. Sabnis and James T. Clemens, “Characterization of electron mobility in the inverted <100> Si surface, " IEDM Tech. Dig., 1979, pp. 18-21.
322. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “An MOS transistor model for analog circuit design”, IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, Oct. 1998.
323. Yannis Tsividis and Guido Masetti, “Problems in precision modeling of the MOS transistor for analog applications, " IEEE Trans. Computer-Aided Design, vol. 3, no. 1, pp. 72-79, Jan. 1984.
324. Christian C. Enz, François Krummenacher and Eric A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications, " J. Analog Integr. Circuits Signal Process., vol. 8, pp. 83-114, July 1995.
325. Y. Tsividis, “Moderate inversion in MOS devices, " Solid-State Electron, vol. 25, no. 11, pp. 1099-1104, Nov. 1982. See also Erratum, ibid, vol. 26, no. 8, p. 823, Aug. 1983.
326. Josef Watts, Colin McAndrew, Christian Enz, Carlos Galup-Montoro, Gennady Gildenblat, Chenming Hu, Ronald van Langevelde, Mitiko Miura-Mattausch, Rafael Rios, Chih-Tang Sah, “Advanced compact models for MOSFETs, " Proc. Workshop on Compact Modeling, Nanotech 2005, pp. 3-12.
327. Mitiko Miura-Mattausch, Uwe Feldmann, Alexander Rahm, Michael Bollu, and Dominique Savignac, “Unified complete MOSFET model for analysis of digital and analog circuits, " IEEE Trans. Computer-Aided Design, vol. 15, no. 1, pp. 1-7, Jan. 1996.
328. R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen, “Physical background of MOS Model 11, " Nat. Lab. Unclassified Report 2003/00239. [Online] Available: http://www.semiconductors.philips.com/Philips_Models/
329. Gennady Gildenblat, Hailing Wang, Ten-Lon Chen, Xin Gu, and Xiaowen Cai, “SP:An advanced surface-potential-based compact MOSFET model, " IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1394-1406, Sep. 2004.
330. Mary Ann Maher and Carver A. Mead, “A physical charge-controlled model for MOS transistors, " in Advanced Research in VLSI, P. Losleben (ed.), MIT Press, Cambridge, MA, pp. 211-229, 1987.
331. Young Hee Byun, Kwyro Lee, and Michael Shur, “Unified charge control model and subthreshold current in heterostructure field effect transistors, " IEEE Electron Device Lett., vol. 11, no. 1, pp. 50-53, Jan. 1990.
332. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “An explicit physical model for the long-channel MOS transistor including smallsignal parameters, " Solid-State Electron., vol. 38, no. 11, pp. 1945-1952, Nov. 1995.
333. J. R. Brews, “A charge-sheet model of the MOSFET, " Solid-State Electron., vol. 21, no. 2, pp. 345-355, Feb. 1978.
334. Hermann K. Gummel and Kumud Singhal, “Inversion charge modeling, " IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 1585-1593, Aug. 2001.
335. Benjamin Iñíguez, David Jiménez, Jaume Roig, Hamdy A. Hamid, Lluís F. Marsal, and Josep Pallarès, “Explicit continuous model for long-channel undoped surrounding gate MOSFETs, " IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1868-1873, Aug. 2005.
336. Giorgio Mugnaini and Giuseppe Iannaccone, “Physics-based compact model of nanoscale MOSFETs-Part I: transition from drift-diffusion to ballistic transport”, IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1795-1801, Aug. 2005.
337. Alexandre Ternes Behr, Márcio Cherem Schneider, Sidnei Noceti Filho, and Carlos Galup Montoro, “Harmonic distortion caused by capacitors implemented with MOSFET gates, " IEEE J. Solid-State Circuits, vol. 27, no. 10, pp. 1470-1475, Oct. 1992.
338. th Brazilian Conference on Microelectronics, 1993, Campinas, Brazil, pp. V7-V12.
339. Carlos Galup-Montoro, Márcio C. Schneider, and Itamar J. B. Loss, “Series-parallel association of FET’s for high gain and high frequency applications, " IEEE J. Solid-State Circuits, vol. 29, no. 9, pp. 1094-1101, Sep. 1994.
340. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “An MOS transistor model for analog circuit design, " IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, Oct. 1998.
341. Application Notes in Home-page Dolphin. [Online]. Available: http://www.dolphin.fr/medal/smash/notes/acm_report.pdf
342. Ana Isabela Araújo Cunha, Márcio Cherem Schneider, and Carlos Galup-Montoro, “Derivation of the unified charge control model and parameter extraction procedure, " Solid-State Electron., vol. 43, no. 3, pp. 481-485, Mar. 1999.
343. Alfredo Arnaud and Carlos Galup-Montoro, “A compact model for flicker noise in MOS transistors for analog circuit design, " IEEE Trans. Electron Devices, vol. 50, no. 8, pp. 1815-1818, Aug. 2003.
344. Carlos Galup-Montoro, Márcio C. Schneider, Hamilton Klimach, and Alfredo Arnaud, “A compact model of MOSFET mismatch for circuit design, " IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1649-1657, Aug. 2005.
345. Matthias Bucher, Analytical MOS Transistor Modelling for Analog Circuit Simulation, PhD Thesis, EPFL, Lausanne, Switzerland, 1999.
346. Jean-Michel Sallese, Matthias Bucher, François Krummenacher, and Pierre Fazan, “Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model, " Solid-State Electron. vol. 47, no. 4, pp. 677-683, Apr. 2003.
347. Jin He, Xuemei Xi, Mansun Chan, Ali Niknejad, and Chenming Hu, “An advanced surface potential-plus MOSFET model, " Proc. Workshop on Compact Modeling, Nanotech 2003, pp. 262-265.
348. Ali Niknejad, BSIM5 presentation. [Online]. Available:http://www.eigroup.org/cmc/next_gen_cmos/bsim5latest.pdf
349. P. P. Guebels and F. Van de Wiele, “A charge sheet model for small geometry MOSFET’s, " IEDM Tech. Dig., 1981, pp. 211-214.
350. Claudio Turchetti and Guido Masetti, “A CAD-oriented analytical MOSFET model for high-accuracy applications, " IEEE Trans. Computer-Aided Design, vol. 3, no. 2, pp. 117-122, Apr. 1984.
351. A. R. Boothroyd, Stan W. Tarasewicz, and Cezary Slaby, “MISNAN - A physically based continuous MOSFET model for CAD applications, " IEEE Trans. Computer-Aided Design, vol. 10, no. 12, pp. 1512-1529, Dec. 1991.
352. Rafael Rios, Sivakumar Mudanai, Wei-Kai Shih, and Paul Packan, “An efficient surface potential solution algorithm for compact MOSFET models, " IEDM Tech. Dig., 2004, pp. 755-758.
353. Mitiko Miura-Mattausch and Hermann Jacobs, “Analytical model for circuit simulation with quarter micron metal oxide semiconductor field effect transistors:subthreshold characteristics, " Jap. J. App. Phys., vol. 29, no. 12, pp. 2279-2282, Dec. 1990.
354. R. M. D. A. Velghe, D. B. M. Klaassen, F. M. Klaassen, “MOS Model 9, " NL-UR 003/94, Philips Electronics N.V. [Online]. Available:http://www.semiconductors.philips.com/Philips_Models/
355. Ronald van Langevelde and François M. Klaassen, “An explicit surface-potentialbased MOSFET model for circuit simulation, " Solid-State Electron., vol. 44, no. 3, pp. 409-418, Mar. 2000.
356. T.-L. Chen and G. Gildenblat, “Analytical approximation for the MOSFET surface potential, " Solid-State Electron., vol. 45, no. 2, pp. 335-339, Feb. 2001.