Analytical solution to a double-gate MOSFET with undoped body

IEEE Electron Device Letters

Volumn 21, Issue 5, 2000, Pages 245-247

  Taur, Yuan ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CHARGE; ELECTRIC POTENTIAL; GATES (TRANSISTOR); ONE DIMENSIONAL; POISSON DISTRIBUTION; PROBLEM SOLVING; SEMICONDUCTING SILICON;

INVERSION CHARGE DENSITY; MOBILE CHARGE; POISSON EQUATION;

MOSFET DEVICES;

EID: 0033732282     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.841310     Document Type: Article

References (6)

1. D. Frank, S. Laux, and M. Fischetti, "Monte Carlo simulation of a 30 nm dual-gate MOSFET: How far can silicon go?," 1992 IEDM Tech. Dig., p. 553.
2. F. Balestra and S. Cristoloveanu et al., "Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance," IEEE Electron Device Lett., vol. EDL-8, p. 410, 1987.
3. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.
4. Y. Taur et al., "CMOS scaling into the nanometer regime," Proc. IEEE, vol. 85, pp. 486-504, 1997.
5. H.-S. P. Wong, D. J. Frank, and P. M. Solomon, "Device design considerations for double-gate, ground-plane, and single-gate ultra-thin SOI MOSFET's at the 25 nm gate length generation," IEDM Tech. Dig., 1998.
6. M. Shoji and S. Horiguchi, "Electronic structures and phononlimited electron mobility of double-gate silicon-on-insulator silicon inversion layers," J. Appl. Phys., vol. 85, pp. 2722-2731, 1999.