-
1
-
-
0020704690
-
An investigation ofthe charge conservation problem for MOSFET circuit simulation
-
P Yang, B. Epler, and P Chatterjee, “An investigation ofthe charge conservation problem for MOSFET circuit simulation,” IEEE J. Solid-State Circuits, vol. 18, pp. 128-138, 1983.
-
(1983)
IEEE J. Solid-State Circuits
, vol.18
, pp. 128-138
-
-
Yang, P.1
Epler, B.2
Chatterjee, P.3
-
2
-
-
0026866294
-
Circuit simulation-the early years
-
May
-
R. Rohrer, “Circuit simulation-the early years,” IEEE Circuits and Devices, pp. 32-37, May 1992.
-
(1992)
IEEE Circuits and Devices
, pp. 32-37
-
-
Rohrer, R.1
-
3
-
-
85008048611
-
Donald o. Pederson
-
June
-
T. S. Perry, “Donald o. Pederson,” IEEE Spectrum, pp. 22-27, June, 1998.
-
(1998)
IEEE Spectrum
, pp. 22-27
-
-
Perry, T.S.1
-
4
-
-
85043334346
-
-
see, For the Macintosh platform
-
A trial version of PSPICE for PC can found in http://www.orcad.comltechserv/pspprint_f.htm. For the Macintosh platform, see http://www.repairfaq.orgIELE/F_Free_Spice. html.
-
A trial version of PSPICE for PC can found
-
-
-
6
-
-
84937744575
-
Modeling and simulation of insulated-gate field-effect transistor switching circuits
-
H. Shichman and D. Hodges, “Modeling and simulation of insulated-gate field-effect transistor switching circuits,” IEEE J. Solid State Circuits, vol. 3, pp. 285-289, 1968.
-
(1968)
IEEE J. Solid State Circuits
, vol.3
, pp. 285-289
-
-
Shichman, H.1
Hodges, D.2
-
7
-
-
0015025121
-
MOS models and circuit simulation
-
gb
-
gb
-
(1971)
RCA Review
, vol.32
, pp. 42-63
-
-
Meyer, J.1
-
8
-
-
85043327023
-
-
University ofCalifomia, Berkeley
-
A. Vladimirescu and S. Liu, The Simulation ofMOS Integrated Circuits Using SPICE2, Electronics Research Laboratory Memo. ERL M80j7, University ofCalifomia, Berkeley, 1980.
-
(1980)
M80j7
-
-
Vladimirescu, A.1
Liu, S.2
-
9
-
-
0018027059
-
A charge-oriented model for MOS transistor capacitances
-
D. Ward and R. Dutton, “A charge-oriented model for MOS transistor capacitances,” IEEE J. Solid-State Circuits, vol. 13, pp. 703-708, 1978.
-
(1978)
IEEE J. Solid-State Circuits
, vol.13
, pp. 703-708
-
-
Ward, D.1
Dutton, R.2
-
10
-
-
0023401686
-
BSIM: Berkeley Short Channel IGFET Model for MOS transistors
-
B. Sheu, D. Sharfetter, Ko, and M. Jeng, “BSIM: Berkeley Short Channel IGFET Model for MOS transistors,” IEEE J. Solid-State Circuits, vol. 22, pp. 558-566, 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.22
, pp. 558-566
-
-
Sheu, B.1
Sharfetter, D.2
Ko, J.M.3
-
11
-
-
0003984119
-
-
Meta-Software, Inc., Campbell, CA
-
HSPICE User’s Manual, Meta-Software, Inc., Campbell, CA, 1996.
-
(1996)
HSPICE User’s Manual
-
-
-
12
-
-
0002746446
-
-
University of California, Berkeley, Electronics Research Laboratory Memorandum No. UCB/ERL M90/90
-
M. Jeng, “Design and modeling of deep submicrometer MOSFETs,” University of California, Berkeley, Electronics Research Laboratory Memorandum No. UCB/ERL M90/90, 1990.
-
(1990)
Design and modeling of deep submicrometer MOSFETs
-
-
Jeng, M.1
-
13
-
-
0003997954
-
-
University of California/Berkeley, Electronics Research Laboratory, See also
-
Y. Cheng et al., “BSIM3 Version 3.0 Manual,” University of California/Berkeley, Electronics Research Laboratory (1995). See also
-
(1995)
BSIM3 Version 3.0 Manual
-
-
Cheng, Y.1
-
14
-
-
85043306597
-
-
University of California/Berkeley, Electronics Research Laboratory
-
J. Huang et al., “B81M3 Manual (Version 2.0),” University of California/Berkeley, Electronics Research Laboratory (1994).
-
(1994)
B81M3 Manual (Version 2.0)
-
-
Huang, J.1
-
15
-
-
0003906956
-
-
University of California, Berkeley, posted on, A recent book also provides valuable information
-
W. Liu et al, “BSIM3v3.2.2 MOSFET Model, User’s Manual,” University of California, Berkeley, posted on http://www-device.eecs.berkeley.edu/-bsim3, 1999. A recent book also provides valuable information
-
(1999)
BSIM3v3.2.2 MOSFET Model, User’s Manual
-
-
Liu, W.1
-
18
-
-
0027814443
-
Compact MOS modeling for analog circuit simulation
-
R. Velghe, D. Klaasen, and F. Klaasen, “Compact MOS modeling for analog circuit simulation,” IEEE International Electron Device Meeting, pp. 485-488, 1993.
-
(1993)
IEEE International Electron Device Meeting
, pp. 485-488
-
-
Velghe, R.1
Klaasen, D.2
Klaasen, F.3
-
19
-
-
0029342165
-
An analytical MOS transistor model valid in all regions of operation and dedicated to low voltage and low current applications
-
C. Enz, F. Krummenacher, and E. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to low voltage and low current applications,” Analog International Circuit and Signal Proceeding, vol. 8, pp. 83-114, 1995.
-
(1995)
Analog International Circuit and Signal Proceeding
, vol.8
, pp. 83-114
-
-
Enz, C.1
Krummenacher, F.2
Vittoz, E.3
-
20
-
-
0029705586
-
Accurate MOS modleing for analog circuit simulation using the EKV model
-
M. Bucher, C. Lallement, C. Enz, F. Krummenacher, “Accurate MOS modleing for analog circuit simulation using the EKV model, IEEE Int. Symp. Circuits and Systems, pp.703706, 1996.
-
(1996)
IEEE Int. Symp. Circuits and Systems
, pp. 703706
-
-
Bucher, M.1
Lallement, C.2
Enz, C.3
Krummenacher, F.4
-
23
-
-
84936527219
-
-
The algorithm can be found in, London: Cambridge University Press, A step-by-step derivation, for a particular electrical problem, of the required coefficients required by the algorithm can be found in, W. Liu, Handbook of 111-V Heterojunction Bipolar Transistors, New York: Wiley, 1998, Chapter 6
-
The algorithm can be found in, W. H. Press, B. P Flannery, S. A. Teukolsky, and W. T. Vetterling, Numerical Recipes, the Art of Scientific Computing. London: Cambridge University Press, 1986. A step-by-step derivation, for a particular electrical problem, of the required coefficients required by the algorithm can be found in, W. Liu, Handbook of 111-V Heterojunction Bipolar Transistors, New York: Wiley, 1998, Chapter 6.
-
(1986)
Numerical Recipes, the Art of Scientific Computing.
-
-
Press, W.H.1
Flannery, B.P.2
Teukolsky, S.A.3
Vetterling, W.T.4
-
24
-
-
0003679682
-
-
Boston: Kluwer Academic, See p. 18 for convergence criteria and p. 173 about the GaAs FET charge model
-
K. Kundert, Designers Guide to SPICE and SPECTRE, Boston: Kluwer Academic, 1995. See p. 18 for convergence criteria and p. 173 about the GaAs FET charge model.
-
(1995)
Designers Guide to SPICE and SPECTRE
-
-
Kundert, K.1
-
25
-
-
0028386555
-
MOSFET modeling for analog circuit CAD: Problems and prospects
-
Y. Tsivids, and K. Suyama, “MOSFET modeling for analog circuit CAD: problems and prospects,” IEEE J. Solid-State Circuits, vol. 29, pp. 210-216, 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, pp. 210-216
-
-
Tsivids, Y.1
Suyama, K.2
-
27
-
-
0004075850
-
-
New York:Wiley, For conversion from y-parameters to s-parameters, see, For gate resistance, see Section 6.5. For charge calculation, see Section 6.1
-
W. Liu, Fundamentals ofIII-V Devices: HBTs, MESFETs, HFETs/HEMTs, New York:Wiley, 1999. For conversion from y-parameters to s-parameters, see p. 249. For gate resistance, see Section 6.5. For charge calculation, see Section 6.1.
-
(1999)
Fundamentals ofIII-V Devices: HBTs, MESFETs, HFETs/HEMTs
, pp. 249
-
-
Liu, W.1
-
28
-
-
0030409592
-
A CAD-compatible non-quasi-static MOSFET model
-
Liu, w., Bowen, C., and Chang, M. (1996) “A CAD-compatible non-quasi-static MOSFET model.” IEEE Int. Electron Device Meeting, pp. 151-154.
-
IEEE Int. Electron Device Meeting
, pp. 151-154
-
-
Liu, W.1
Bowen, C.2
Chang, M.3
-
29
-
-
0021482325
-
A compact IGFET charge model
-
B. Sheu, D. Sharfetter, C. Hu, and D. Pederson, “A compact IGFET charge model,” IEEE Trans. Circuits Systems, vol. 31, pp. 745-748, 1984.
-
(1984)
IEEE Trans. Circuits Systems
, vol.31
, pp. 745-748
-
-
Sheu, B.1
Sharfetter, D.2
Hu, C.3
Pederson, D.4
-
30
-
-
0024749934
-
The Meyer model revisited: Why is charge not conserved?
-
M. Cirit, “The Meyer model revisited: why is charge not conserved?,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 1033-1037, 1989.
-
(1989)
IEEE Trans. Computer-Aided Design
, vol.8
, pp. 1033-1037
-
-
Cirit, M.1
-
31
-
-
0023292335
-
GaAs FET device and circuit simulation in SPICE
-
It is believed that this paper describes the “Staz model” mentioned on p. 173 of Ref.
-
H. Statz, P Newman, I. Smith, R. Pucel, and H. Haus, “GaAs FET device and circuit simulation in SPICE,” IEEE Trans. Electron Devices, vol. 34, pp. 160-168, 1987. It is believed that this paper describes the “Staz model” mentioned on p. 173 of Ref.
-
(1987)
IEEE Trans. Electron Devices
, vol.34
, pp. 160-168
-
-
Statz, H.1
Newman, P.2
Smith, I.3
Pucel, R.4
Haus, H.5
-
32
-
-
0031627636
-
Three new mathematical techniques for field effect transistor modeling and analysis
-
A. Snider, “Three new mathematical techniques for field effect transistor modeling and analysis,” Proc. IEEE Int. Caracas Con! on Devices, Circuits, and Systems, pp. 65-68, 1998.
-
(1998)
Proc. IEEE Int. Caracas Con! on Devices, Circuits, and Systems
, pp. 65-68
-
-
Snider, A.1
-
33
-
-
0029404050
-
Charge conservation and the transcapacitance element: An exposition
-
A. Snider, “Charge conservation and the transcapacitance element: an exposition,” IEEE Trans. Education, vol. 38, pp. 376-379, 1995.
-
(1995)
IEEE Trans. Education
, vol.38
, pp. 376-379
-
-
Snider, A.1
-
35
-
-
0029180063
-
Estimating key parameters in the EKV MOST model for analog design and simulation
-
G. Machado, C. Enz, and M. Bucher, “Estimating key parameters in the EKV MOST model for analog design and simulation,” IEEE Int. Symp. Circuits and Systems, pp. 1588-1591, 1995.
-
(1995)
IEEE Int. Symp. Circuits and Systems
, pp. 1588-1591
-
-
Machado, G.1
Enz, C.2
Bucher, M.3
-
36
-
-
0022795975
-
Table lookup MOSFET capacitance model for short-channel devices
-
T. Shima, “Table lookup MOSFET capacitance model for short-channel devices,” IEEE Trans. Computer-Aided Design, vol. 5, pp. 624-632, 1986.
-
(1986)
IEEE Trans. Computer-Aided Design
, vol.5
, pp. 624-632
-
-
Shima, T.1
-
37
-
-
0020738150
-
Table look-up MOSFET modeling system using a 2D device simulator and monotonic piecewise curbic interpolation
-
T. Shima, H. Yamada, and R. Dang, “Table look-up MOSFET modeling system using a 2D device simulator and monotonic piecewise curbic interpolation,” IEEE Trans. Computer-Aided Design, vol. 2 pp. 121-126, 1983.
-
(1983)
IEEE Trans. Computer-Aided Design
, vol.2
, pp. 121-126
-
-
Shima, T.1
Yamada, H.2
Dang, R.3
-
38
-
-
0027684654
-
A universal large/small signal 3-terminal FET model using a nonquasi-static charge-based appraoch
-
R. Daniels, A. Yang, and J. Harrang, “A universal large/small signal 3-terminal FET model using a nonquasi-static charge-based appraoch,” IEEE Trans. Electron Devices, vol. 40, pp. 1723-1729, 1993.
-
(1993)
IEEE Trans. Electron Devices
, vol.40
, pp. 1723-1729
-
-
Daniels, R.1
Yang, A.2
Harrang, J.3
-
39
-
-
0026395570
-
Technology Independent large signal non quasi-static FET models by direct construction from automatically characterized device data
-
Stuttgart, Germany
-
D. Root, S. Fan, and J.Meyer, “Technology Independent large signal non quasi-static FET models by direct construction from automatically characterized device data,” Proc. 21st European Microwave Conf., Stuttgart, Germany, pp. 927-932, 1991.
-
(1991)
Proc. 21st European Microwave Conf.
, pp. 927-932
-
-
Root, D.1
Fan, S.2
Meyer, J.3
-
40
-
-
0003628654
-
-
New York: Wiley, See Chapter 15 for the pad test structure and de-embedding procedure
-
W. Liu, Handbook ofIII-V Heterojunction Bipolar Transistors, New York: Wiley, 1998. See Chapter 15 for the pad test structure and de-embedding procedure.
-
(1998)
Handbook ofIII-V Heterojunction Bipolar Transistors
-
-
Liu, W.1
-
43
-
-
0025519325
-
Relationship between measured and intrinsic conductances of MOSFETs
-
S. Cserveny, “Relationship between measured and intrinsic conductances of MOSFETs,” IEEE Trans. Electron Devices, vol. 17, pp. 2413-2414, 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.17
, pp. 2413-2414
-
-
Cserveny, S.1
-
44
-
-
0003628654
-
-
Alot ofthe matrix manipulation can be seen in, New York: Wiley, Chapter 8, especially § 8-13 and § 8-14
-
Alot ofthe matrix manipulation can be seen in W. Liu, Handbook ofIII-VHeterojunction Bipolar Transistors, New York: Wiley, 1998. Chapter 8, especially § 8-13 and § 8-14.
-
(1998)
Handbook ofIII-VHeterojunction Bipolar Transistors
-
-
Liu, W.1
-
45
-
-
84867244371
-
A general model for fa spectral density random noise with special reference to Flicker noise lit
-
March
-
D. Harford, “A general model for fa spectral density random noise with special reference to Flicker noise lit:" IEEEProceeding, vol. 56, p. 251, March 1968.
-
(1968)
IEEEProceeding
, vol.56
, pp. 251
-
-
Harford, D.1
-
46
-
-
0022288585
-
High frequency noise in fine line NMOS field effect transistors
-
R. Jindal, “High frequency noise in fine line NMOS field effect transistors,” Proc. IEEE International Electron Devices Meeting, pp. 68-71, 1985.
-
(1985)
Proc. IEEE International
, pp. 68-71
-
-
Jindal, R.1
-
47
-
-
84889322536
-
High-Speed or Low-Voltage Low-Power Operations
-
S. Sze and c. Y. Chang, ed, New York: Wiley
-
I. Chen, and W. Liu, “High-Speed or Low-Voltage Low-Power Operations,” in S. Sze and c. Y. Chang, ed. ULSIDevices, New York: Wiley, pp. 547-630, 2000.
-
(2000)
ULSIDevices
, pp. 547-630
-
-
Chen, I.1
Liu, W.2
-
48
-
-
0029543661
-
A physical compact MOSFET model, including quantum mechanical effects, for statistical circuit design applications
-
R. Rios, N. Arora, C. Huang, N. Khalil, J. Faricelli, and L. Gruber, “A physical compact MOSFET model, including quantum mechanical effects, for statistical circuit design applications,” IEEE International Electron Device Meeting, pp. 937-940, 1995.
-
(1995)
IEEE International Electron Device Meeting
, pp. 937-940
-
-
Rios, R.1
Arora, N.2
Huang, C.3
Khalil, N.4
Faricelli, J.5
Gruber, L.6
-
49
-
-
85043314291
-
-
Memorandum No. UCB/ERL M98/4, University of California, Berkeley, July
-
W Liu, X. Jin, Y. King and C. Hu, “An accurate MOSFET intrinsic capacitance model considering quantum mechanical effect for BSIM3v3.2,” Memorandum No. UCB/ERL M98/4, University of California, Berkeley, July, 1998.
-
(1998)
An accurate MOSFET intrinsic capacitance model considering quantum mechanical effect for BSIM3v3.2
-
-
Liu, W.1
Jin, X.2
King, Y.3
Hu, C.4
-
50
-
-
4243547221
-
A unified substrate current model for weak and strong impact ionizatin in sub-0.25 f.lf.l NMOS devices
-
S. Ramaswamy, A. Amerasekera, and M. Chang, “A unified substrate current model for weak and strong impact ionizatin in sub-0.25 f.lf.l NMOS devices,” IEEE International Electron Device Meeting, pp. 885-888, 1997.
-
(1997)
IEEE International Electron Device Meeting
, pp. 885-888
-
-
Ramaswamy, S.1
Amerasekera, A.2
Chang, M.3
-
51
-
-
0032595355
-
Parasitic capacitance of submicrometer MOSFET’s
-
K. Suzuki, “Parasitic capacitance of submicrometer MOSFET’s, IEEE Trans. Electron Devices, vol. 46, pp. 1895-1900, 1999. .
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, pp. 1895-1900
-
-
Suzuki, K.1
-
52
-
-
0004005306
-
-
2nd ed., New York: Wiley, For the discussion on carrier lifetime’s temperature dependence, see, For the discussion on mobility’s temperature dependence, see p. 28
-
S. Sze, Physics of Semiconductor Devices, 2nd ed., New York: Wiley, 1981. For the discussion on carrier lifetime’s temperature dependence, see p. 88. For the discussion on mobility’s temperature dependence, see p. 28.
-
(1981)
Physics of Semiconductor Devices
, pp. 88
-
-
Sze, S.1
-
53
-
-
0003750001
-
-
New York: McGraw-Hill, For the discussion on narrow-width effects, see Eq. (5.4.22)
-
Y. Tsividis, Operation and Modeling of the MOS Transistor, New York: McGraw-Hill, 1987. For the discussion on narrow-width effects, see Eq. (5.4.22).
-
(1987)
Operation and Modeling of the MOS Transistor
-
-
Tsividis, Y.1
-
54
-
-
0018683243
-
Characterization of electron velocity in the inverted (100) Si surface
-
A. Sabnis, and J. Clemens, “Characterization of electron velocity in the inverted (100) Si surface,” IEEE International Electron Devices Meeting, pp. 18-21, 1979.
-
(1979)
IEEE International Electron Devices Meeting
, pp. 18-21
-
-
Sabnis, A.1
Clemens, J.2
-
55
-
-
0028419315
-
An analytic polysilicon depletion effect model for MOSFETs
-
R. Rios, N. Arora, and C. Huang, “An analytic polysilicon depletion effect model for MOSFETs,” IEEE Electron Device Lett., vol. 15, pp. 129-131,1994.
-
(1994)
IEEE Electron Device Lett.
, vol.15
, pp. 129-131
-
-
Rios, R.1
Arora, N.2
Huang, C.3
-
56
-
-
0026938337
-
-
D. Costa, and J. Harris, Low-frequency noise properties of Npn AIGaAs/GaAs heterojunction bipolar transistors,” IEEE Trans. Electron Devices, vol. 39, pp. 2383-2394, 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, pp. 2383-2394
-
-
Costa, D.1
Harris, J.2
-
57
-
-
0022688857
-
Inversion-layer capacitance and mobility of very thin gate-oxide MOSFETs
-
M. Liang, J. Choi, P. Ko, and C. Hu, “Inversion-layer capacitance and mobility of very thin gate-oxide MOSFETs,” IEEE Trans. Electron Devices, vol. 33, p. 409, 1986.
-
(1986)
IEEE Trans. Electron Devices
, vol.33
, pp. 409
-
-
Liang, M.1
Choi, J.2
Ko, P.3
Hu, C.4
-
58
-
-
85043303050
-
-
The official BSIM3 website is
-
The official BSIM3 website is: http://www-device.eecs.berkeley.eduJ--bsim3
-
-
-
-
59
-
-
0021477881
-
Switch-induced error voltage on a switched capacitor
-
B. Sheu, and C. Hu, “Switch-induced error voltage on a switched capacitor,” IEEE J Solid-State Circuits, vol. 19, pp. 519-525, 1984.
-
(1984)
IEEE J Solid-State Circuits
, vol.19
, pp. 519-525
-
-
Sheu, B.1
Hu, C.2
-
60
-
-
0030409592
-
A CAD-compatible non-quasi-static MOSFET model
-
W. Liu, C. Bowen, and M. Chang, “A CAD-compatible non-quasi-static MOSFET model,” IEEE International Electron DeviceMeeting, pp. 151-154, 1996.
-
(1996)
IEEE International Electron DeviceMeeting
, pp. 151-154
-
-
Liu, W.1
Bowen, C.2
Chang, M.3
-
61
-
-
0027684654
-
A universal large/small signal 3-terminaI FEr model using a nonquasi-static charge-based approach
-
R. Daniels, A. Yang, and J. Harrang, “A universal large/small signal 3-terminaI FEr model using a nonquasi-static charge-based approach,” IEEE Trans. Electron Devices, vol. 40, pp. 1723-1729, 1993.
-
(1993)
IEEE Trans. Electron Devices
, vol.40
, pp. 1723-1729
-
-
Daniels, R.1
Yang, A.2
Harrang, J.3
-
62
-
-
85043315368
-
-
dated October 1997, apparently havingbeen copiedand forwarded several times. It seemsthat the original author of the mail, as well as the authorwho documents this problem, is D. Foty, of Gilgamensh Associates
-
The Killer NOR-Gate first came to the author’s attention in a broadcast e-mail, dated October 1997, apparently havingbeen copiedand forwarded several times. It seemsthat the original author of the mail, as well as the authorwho documents this problem, is D. Foty, of Gilgamensh Associates, http.z/www.sover.net/r-dfoty
-
The Killer NOR-Gate first came to the author’s attention in a broadcast e-mail
-
-
-
64
-
-
85043351315
-
RF CMOS modeling, Workshop on Advances in Analog Circuit Design
-
(The statement that ri is Re(-I/Ygs, NQs) in the paper is likely a typo.)
-
L. Tiemeijer, L. de Maaijer, R. van Langevelde, A. Scholten, and D. Klaassen, “RF CMOS modeling, Workshop on Advances in Analog Circuit Design, AACD Proc., 1999. (The statement that ri is Re(-I/Ygs, NQs) in the paper is likely a typo.)
-
(1999)
AACD Proc.
-
-
Tiemeijer, L.1
de Maaijer, L.2
van Langevelde, R.3
Scholten, A.4
Klaassen, D.5
-
65
-
-
84886447987
-
RF MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model
-
W. Liu, R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal, and J. Mattia, “RF MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model,” IEEE Int. Electron Device Meeting, 1997.
-
IEEE Int. Electron Device Meeting, 1997.
-
-
Liu, W.1
Gharpurey, R.2
Chang, M.C.3
Erdogan, U.4
Aggarwal, R.5
Mattia, J.6
-
66
-
-
84886448019
-
Feasibility of using W/TiN as metal gate for conventional 0.13 urn CMOS technology and beyond
-
I.Hu, H. Yang, R. Kraft, A. Rotondaro, S. Hattangady, W. Lee, A. Chapman, C. Chao, A. Chatterjee, M. Hanratty, M. Rodder, and I. Chen, “Feasibility of using W/TiN as metal gate for conventional 0.13 urn CMOS technology and beyond,” IEEE Int. Electron Device Meeting, pp. 825-828,1997.
-
(1997)
IEEE Int. Electron Device Meeting, pp.
, pp. 825-828
-
-
Hu, I.1
Yang, H.2
Kraft, R.3
Rotondaro, A.4
Hattangady, S.5
Lee, W.6
Chapman, A.7
Chao, C.8
Chatterjee, A.9
Hanratty, M.10
Rodder, M.11
Chen, I.12
-
67
-
-
0032049333
-
Transistor transient studies including transcapacitive current and distributive gate resistance for inverter circuits
-
W. Liu, and M. C. Chang, “Transistor transient studies including transcapacitive current and distributive gate resistance for inverter circuits,” IEEE Trans. Circuits Systems-I:Fundamental Theory Appl., vol. 45, pp. 416-422, 1998.
-
(1998)
IEEE Trans. Circuits Systems-I:Fundamental Theory Appl.
, vol.45
, pp. 416-422
-
-
Liu, W.1
Chang, M.C.2
-
69
-
-
84889322536
-
High-speed or Low-voltage low-power operations
-
S. Sze and C. Y. Chang, ed, New York: Wiley
-
I. Chen, and W. Liu, “High-speed or Low-voltage low-power operations,” in S. Sze and C. Y. Chang, ed. ULSI Devices, New York: Wiley, pp. 547-630, 2000.
-
(2000)
ULSI Devices
, pp. 547-630
-
-
Chen, I.1
Liu, W.2
-
70
-
-
0343123752
-
BSIM3 MOSFET model accuracy for RF circuit simulation
-
S. Tin, A. Osman, and K. Mayaram, “BSIM3 MOSFET model accuracy for RF circuit simulation,” IEEE RAWCON Proc. pp. 351-354, 1998.
-
(1998)
IEEE RAWCON Proc.
, pp. 351-354
-
-
Tin, S.1
Osman, A.2
Mayaram, K.3
-
71
-
-
0033720759
-
Test structure for universal estimation of MOSFET substrate effects at gigahertz frequencies
-
T. Kolding, “Test structure for universal estimation of MOSFET substrate effects at gigahertz frequencies,” Proc. Int. Cont on Microelectronic Test Structures, pp. 106-111, 2000.
-
(2000)
Proc. Int. Cont on Microelectronic Test Structures
, pp. 106-111
-
-
Kolding, T.1
-
73
-
-
0029271410
-
An accurate intrinsic capacitance modeling for deep submicrometer MOSFET’s
-
D. Cho, S. Kang, K. Kim, and S. Lee, “An accurate intrinsic capacitance modeling for deep submicrometer MOSFET’s,” IEEE Trans. Electron Devices, vol. 42, pp. 540-548, 1995.
-
(1995)
IEEE Trans. Electron Devices
, vol.42
, pp. 540-548
-
-
Cho, D.1
Kang, S.2
Kim, K.3
Lee, S.4
-
74
-
-
0022811203
-
High frequency noise measurement on FET’s with small dimensions
-
A. Abidi, “High frequency noise measurement on FET’s with small dimensions,” IEEE Trans. Electron Devices, vol. 33, pp. 1801-1805, 1986.
-
(1986)
IEEE Trans. Electron Devices
, vol.33
, pp. 1801-1805
-
-
Abidi, A.1
-
75
-
-
85043338752
-
Recent developments in BSIM for CMOS RF ac and noise modeling
-
I. Ou, X. Jin, P Gray, and C. Hu, “Recent developments in BSIM for CMOS RF ac and noise modeling,” Proc. Workshop on Advances in Analog Circuit Design (AACD), 1999.
-
(1999)
Proc. Workshop on Advances in Analog Circuit Design (AACD)
-
-
Ou, I.1
Jin, X.2
Gray, P.3
Hu, C.4
-
77
-
-
0017453673
-
A review of some charge transport properties of silicon
-
C. Jacobini, “A review of some charge transport properties of silicon,” Solid-State Electronics, vol. 20, pp. 77-89, 1977.
-
(1977)
Solid-State Electronics
, vol.20
, pp. 77-89
-
-
Jacobini, C.1
-
78
-
-
85043318821
-
-
Private communication with J. Leete, U.C.L.A
-
Private communication with J. Leete, U.C.L.A.
-
-
-
-
82
-
-
33747154085
-
MOSFET’s negative transconductance at roomtemperature
-
R. Versari, and B. Ricco, “MOSFET’s negative transconductance at roomtemperature,” IEEE Trans. Electron Devices, vol. 46, pp. 1189-1195,1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, pp. 1189-1195
-
-
Versari, R.1
Ricco, B.2
-
83
-
-
0026896291
-
Designfor suppression of gate-induced drain leakage in LDD MOSFET’s using a quasi-two-dimensional analytical model
-
S. Parke, J. Moon, H. Wann, P Ko, and C. Hu, “Designfor suppression of gate-induced drain leakage in LDD MOSFET’s using a quasi-two-dimensional analytical model,” IEEE Trans. Electron Devices, vol. 39, pp. 1694-1703, 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, pp. 1694-1703
-
-
Parke, S.1
Moon, J.2
Wann, H.3
Ko, P.4
Hu, C.5
-
85
-
-
85043328962
-
-
See, for the latest development
-
See http://www-device.eecs.berkeley.edu/I’V bsim3 for the latest development.
-
-
-
-
86
-
-
44149120173
-
Modeling of pocket implanted MOSFETs for anomalous analog behavior
-
K. Cao et al., “Modeling of pocket implanted MOSFETs for anomalous analog behavior,” Proc. IEEE International Electron Device Meeting, 1999.
-
(1999)
Proc. IEEE International Electron Device Meeting
-
-
Cao, K.1
-
87
-
-
0004075850
-
-
New York: Wiley, See Section 6.5 for the distributed gate resistance. See Section 3.7 for distributed base resistance. See Eq. (5-133) for the expression of IDs, 0 (written as IDs, sat in the reference)
-
W. Liu, Fundamentals of III-V Devices: HBTs, MESFETs, and HFETs/HEMTs, New York: Wiley, 1999. See Section 6.5 for the distributed gate resistance. See Section 3.7 for distributed base resistance. See Eq. (5-133) for the expression of IDs, 0 (written as IDs, sat in the reference).
-
(1999)
Fundamentals of III-V Devices: HBTs, MESFETs, and HFETs/HEMTs
-
-
Liu, W.1
-
89
-
-
4243836469
-
An effective gate resistance model for CMOS RF and noise modeling
-
X. Jin, J. Ou, C. Chen, W. Liu, P Gray, and C. Hu, “An effective gate resistance model for CMOS RF and noise modeling,” IEEEInternational Electron DeviceMeeting, pp. 961964, 1998.
-
(1998)
IEEEInternational Electron DeviceMeeting
, pp. 961964
-
-
Jin, X.1
Ou, J.2
Chen, C.3
Liu, W.4
Gray, P.5
Hu, C.6
-
90
-
-
84886447987
-
RF MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model
-
W. Liu, R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal, and J. Mattia, “RF MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model,” IEE EInt. Electron DeviceMeeting, 1997.
-
IEE EInt. Electron DeviceMeeting, 1997.
-
-
Liu, W.1
Gharpurey, R.2
Chang, M.C.3
Erdogan, U.4
Aggarwal, R.5
Mattia, J.6
-
91
-
-
85043316468
-
Noise partition-an accurate short-channel MOSFET thermal noise model for RF low noise applications
-
to be published
-
X. Jin, J. Ou, K. Cao, W. Liu, and C. Hu, “Noise partition-an accurate short-channel MOSFET thermal noise model for RF low noise applications,” to be published.
-
-
-
Jin, X.1
Ou, J.2
Cao, K.3
Liu, W.4
Hu, C.5
-
93
-
-
84938443557
-
Gate noise in field effect transistors at moderately high frequencies
-
A. van der Ziel, “Gate noise in field effect transistors at moderately high frequencies,” IEEEProc., vol. 51, pp. 461-467, 1963
-
(1963)
IEEEProc.
, vol.51
, pp. 461-467
-
-
van der Ziel, A.1
-
94
-
-
0033725602
-
Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling
-
W. Lee, and C. Hu, “Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling,” IEEE VLSITech. Digest, pp. 198-199, 2000.
-
(2000)
IEEE VLSITech. Digest
, pp. 198-199
-
-
Lee, W.1
Hu, C.2
-
95
-
-
0032662220
-
Modeling study ofultrathin gate oxides using direct tunneling current and C-V measurements in MOS devices
-
N. Yang, W. Henson, J.Hauser, and J. Wortman, “Modeling study ofultrathin gate oxides using direct tunneling current and C-V measurements in MOS devices,” IEEE Trans. Electron Dev., pp. 1464-1471, 1999.
-
(1999)
IEEE Trans. Electron Dev.
, pp. 1464-1471
-
-
Yang, N.1
Henson, W.2
Hauser, J.3
Wortman, J.4
-
96
-
-
84889322536
-
High-speed or low-voltage, low-power operations
-
C. Y. Chang and S. Sze (eds), New York: Wiley
-
I. C. Chen and W. Liu, “High-speed or low-voltage, low-power operations,” in C. Y. Chang and S. Sze (eds), ULSIDevices, New York: Wiley, pp. 566-567, 2000.
-
(2000)
ULSIDevices
, pp. 566-567
-
-
Chen, I.C.1
Liu, W.2
-
98
-
-
0004075850
-
-
NewYork:Wiley, O Appendices A and B
-
W. Liu, Fundamentals ofIII-VDevices: HBTs, MESFETs, and HFET’s/HEMTs, NewYork:Wiley, 1999 O Appendices A and B.
-
Fundamentals ofIII-VDevices: HBTs, MESFETs, and HFET’s/HEMTs
, vol.1999
-
-
Liu, W.1
-
100
-
-
0028747636
-
A relation time approach to model the nonquasi- static transient effects in MOSFETs
-
M. Chan, K. Hui, R. Neff, C. Hu, and Ko, “A relation time approach to model the nonquasi- static transient effects in MOSFETs,” IEEE Int. Electron Devices Meeting, pp. 169-172, 1994.
-
(1994)
IEEE Int. Electron Devices Meeting
, pp. 169-172
-
-
Chan, M.1
Hui, K.2
Neff, R.3
Hu, C.K.4
-
101
-
-
84966235265
-
-
London: Cambridge University Press
-
W. Press, B. Flannery, S. TeukoIsky, and W. Vetterling, Numerical Recipes, the Art of Scientific Computing. London: Cambridge University Press, 1986.
-
(1986)
Numerical Recipes, the Art of Scientific Computing.
-
-
Press, W.1
Flannery, B.2
TeukoIsky, S.3
Vetterling, W.4
-
102
-
-
0028427016
-
Microscopic noise modeling and macroscopic noise models: How good a connection?
-
opt• (Communication with J.S.Goo of Stanford University.) See also
-
opt• (Communication with J. S. Goo of Stanford University.) See also, E Danneville, H. Happy, G. Dambrine, J. Belquin, and A. Cappy, “Microscopic noise modeling and macroscopic noise models: how good a connection?" IEEE Trans. Electron Devices, vol. 41, pp. 779-786, 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, pp. 779-786
-
-
Danneville, E.1
Happy, H.2
Dambrine, G.3
Belquin, J.4
Cappy, A.5
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