Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation

IEEE Transactions on Electron Devices

Volumn 49, Issue 10, 2002, Pages 1783-1789

  Ueno, Hioraki ^b   Kitamaru, Daisuke ^b   Morikawa, Keiichi ^c   Tanaka, Masayasu ^b   Miura Mattausch, Mitiko ^a,b   Mattausch, Hans Juergen ^a   Kumashiro, Shigetaka ^a,d   Yamaguchi, Tetsuya ^e   Yamashita, Kyoji ^f   Nakayama, Noriaki ^a,c  

^a IEEE

^b HIROSHIMA UNIVERSITY   (Japan)

^c SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

^d NEC CORPORATION   (Japan)

^e TOSHIBA CORPORATION   (Japan)

^f PANASONIC CORPORATION   (Japan)

Author keywords

Circuit simulation; Pocket implanted MOSFETs; Reverse short channel effect; Threshold voltage model

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SIMULATION; MATHEMATICAL MODELS; PARAMETER ESTIMATION; SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE;

MAXIMUM DOPING CONCENTRATION; POCKET IMPLANT TECHNOLOGY; SHORT CHANNEL EFFECT;

MOSFET DEVICES;

EID: 0036772199     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.803633     Document Type: Article

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