High performance fully-depleted tri-gate CMOS transistors

IEEE Electron Device Letters

Volumn 24, Issue 4, 2003, Pages 263-265

  Doyle, B S ^a   Datta, S ^a   Doczy, M ^a   Hareland, S ^a   Jin, B ^a   Kavalieros, J ^a   Linton, T ^a   Murthy, A ^a   Rios, R ^a   Chau, R ^a  

^a INTEL CORPORATION   (United States)

Author keywords

CMOSFET logic devices; CMOSFETs; MOS devices; MOSFET logic devices; MOSFETs

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; THREE DIMENSIONAL; THRESHOLD VOLTAGE; TRANSMISSION ELECTRON MICROSCOPY;

FULL DEPLETION; TRI-GATE CMOS TRANSISTOR;

MOSFET DEVICES;

EID: 0038104277     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.810888     Document Type: Letter

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