A compact model of MOSFET mismatch for circuit design

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 8, 2005, Pages 1649-1657

  Galup Montoro, Carlos ^a   Schneider, Márcio C ^a   Klimach, Hamilton ^b   Arnaud, Alfredo ^c  

^a FEDERAL UNIVERSITY OF SANTA CATARINA   (Brazil)

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^c UNIVERSIDAD CATÓLICA DEL URUGUAY   (Uruguay)

Author keywords

Analog design; Compact models; Matching; Mismatch; MOSFET

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DOPING (ADDITIVES); ELECTRIC CURRENTS; GATES (TRANSISTOR); MATHEMATICAL MODELS; NETWORKS (CIRCUITS); RANDOM PROCESSES; TRANSISTORS;

ANALOG DESIGN; COMPACT MODELS; MATCHING; MISMATCH;

MOSFET DEVICES;

EID: 23744470875     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.852045     Document Type: Article

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