SOI technology for the GHz era

IBM Journal of Research and Development

Volumn 46, Issue 2-3, 2002, Pages 121-131

  Shahidi, G G ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE STRUCTURES; STATIC RANDOM ACCESS STORAGE;

EMBEDDED MEMORIES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0036508380     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.462.0121     Document Type: Article

References (27)

1. A room temperature 0.1 μm CMOS on SOI
2. A 0.25 μm CMOS on SOI and its application to 4 Mb SRAM
3. A 0.22 μm CMOS-SOI technology with a Cu BEOL
4. A 0.18 μm CMOS on SOI technology
5. A high performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric
6. Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology
7. Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's
8. Transient pass-transistor leakage current in SOI MOSFET's
9. History dependence of non-fully depleted (NFD) digital SOI circuits
10. Partially depleted SOI technology for digital logic
11. Controlling floating-body effects for 0.13 μm and 0.10 μm SOI CMOS
12. A 660 MHz 64b SOI processor with Cu interconnects
13. A 0.2 μm 1.8 V SOI 550 MHz 64b PowerPC microprocessor with copper interconnects
14. A 2nd generation 440 ps SOI 64b adder
15. eff CMOS SOI with Cu interconnects
16. 0.25 micron 1.8 V 1 GHz PLL for SOI microprocessors
17. Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors
18. A high performance 0.13 μm SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL
19. Physical design of a fourth-generation POWER GHz microprocessor
20. SOI CMOS for low power and RF
21. Networking applications of a high performance 0.13-μm SOI CMOS technology
22. High performance sub-40 nm CMOS devices on SOI for the 70 nm technology node
23. Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI
24. 0.25 μm merged bulk DRAM and SOI logic using patterned SOI
25. A 0.13 μm high-performance SOI logic technology with embedded DRAM for system-on-a-chip application