A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation

IEEE Transactions on Electron Devices

Volumn 44, Issue 2, 1997, Pages 277-287

  Cheng, Yuhua ^a,b   Jeng, Min Chie ^a   Liu, Zhihong ^c   Huang, Jianhui ^b   Chan, Mansun ^d   Chen, Kai ^e   Ko, Ping Keung ^a   Hu, Chenming ^f  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c CADENCE DESIGN SYSTEMS   (United States)

^d BTA Technology Inc   (United States)

^e INTEL CORPORATION   (United States)

^f HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC RESISTANCE; FERMI LEVEL; MODELS; NETWORKS (CIRCUITS); SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; SIMULATION; VLSI CIRCUITS;

ANALOG CIRCUIT; CHANNEL LENGTH; CHANNEL WIDTH; CURRENT CHARACTERISTIC; GATE OXIDE THICKNESS;

MOSFET DEVICES;

EID: 0031078092     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.557715     Document Type: Article

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