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Solid-State Electronics

Volumn 46, Issue 3, 2002, Pages 407-416

Electrical characterization and modeling of MOS structures with an ultra-thin oxide

(5) Clerc, R a De Salvo, B b Ghibaudo, G a Reimbold, G b Pananakakis, G a

a CNRS (France)

b CEA LETI (France)

Author keywords

Capacitance; MOS structure; Tunneling; Ultra thin oxide

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIELECTRIC MATERIALS; GATES (TRANSISTOR); ULTRATHIN FILMS;

GATE CURRENTS; ULTRA-THIN OXIDES;

MOS DEVICES;

EID: 0036498447 PISSN: 00381101 EISSN: None Source Type: Journal
DOI: 10.1016/S0038-1101(01)00113-7 Document Type: Article

Times cited : (26)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.