The development of the next generation BSIM for sub-100nm mixed-signal circuit simulation

2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004

Volumn 2, Issue , 2004, Pages 70-73

  Xi, Xuemei ^a   He, Jin ^a   Dunga, Mohan ^a   Lin, Chung Hsun ^a   Heydari, Babak ^a   Wan, Hui ^a   Chan, Mansun ^a   Niknejad, Ali M ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Compact modeling; MOSFETs; Small dimensional effects; Surface potential plus model

Indexed keywords

COMPACT MODELING; SMALL DIMENSIONLESS EFFECTS; SURFACE POTENTIAL-PLUS MODEL;

BAND STRUCTURE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CHARGE; INTEGRATED CIRCUITS; LOGIC DESIGN; MATHEMATICAL MODELS; NETWORKS (CIRCUITS); SEMICONDUCTOR DOPING;

MOSFET DEVICES;

EID: 6344260497     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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2. Y. Cheng, etal., IEEE Trans. on Electron Devices, Vol. 44, No. 2, pp. 277-287, February 1997.
3. BSIM,http://www.device.eecs.berkeley.edu/~bsim3.
4. G. Gildenblat, etal., pp233-240, CICC2003.
5. M. Miura-Mattausch, etal., pp258-261, WCM2003
6. M. Bucher, etal, pp. 670-673 WCM2002.
7. C. Galup-Montoro, etal., pp. 254-257, WCM2003.
8. H. Gummel and K.Singhal. IEEE Trans on Electron Devices, vol. 48, 1585-1593, 2001.
9. J. He, etal, pp.262-265, WCM2003