Physics-based compact model of nanoscale MOSFETs - Part I: Transition from drift-diffusion to ballistic transport

IEEE Transactions on Electron Devices

Volumn 52, Issue 8, 2005, Pages 1795-1801

  Mugnaini, Giorgio ^a   Iannaccone, Giuseppe ^a  

^a UNIVERSITY OF PISA   (Italy)

Author keywords

Ballistic transport; Compact models; Lambert W function; Nanoscale MOSFETs; Quantum confinement

Indexed keywords

CARRIER MOBILITY; ELECTRON TRANSPORT PROPERTIES; MATHEMATICAL MODELS; NANOSTRUCTURED MATERIALS; QUANTUM ELECTRONICS; SEMICONDUCTOR DEVICE MODELS;

BALLISTIC TRANSPORT; COMPACT MODELS; NANOSCALE MOSFETS; QUANTUM CONFINEMENT;

MOSFET DEVICES;

EID: 23344450719     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.851827     Document Type: Article

References (34)

1. G. Gildenblat, T.-L. Chen, X. Gum, H. Wang, and X. Cai, "SP: An advanced surface-potential-based compact MOSFET model," in Proc. Custom Integrated Circuits Conf., Sep. 2003, pp. 233-240.
2. Y. Cheng, M.-C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P. K. Ko, and C. Hu, "A physical and scalable I-V model in BSIM3v3 for analog/ digital circuit simulation," IEEE Trans. Electron Devices, vol. 45, no. 2, pp. 277-287, Feb. 1997.
3. P. Bendix, "Detailed comparison of the SP2001, EKV, and BSIM3 models," in Proc. Int. Conf. Modeling Simulation Microsystems, Apr. 2002, pp. 649-652.
4. D. B. M. Klaassen et al., The MOS Model, Level 1101: Philips Research Laboratories, Apr. 2001.
5. M. Miura-Mattausch, H. Ueno, M. Tanaka, H. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "HiSIM: A MOSFET model for circuit simulation connecting circuit performance with technology," in IEDM Tech. Dig., Dec. 2002, pp. 109-112.
6. C. C. Enz, F. Krummenacher, and E. Vittoz, "An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-power applications," Analog Integr. Circuits Signal Process. J., no. 8, pp. 83-114, Jul. 1995.
7. C.-K. Park, C.-Y. Lee, K. Lee, B.-J. Moon, Y.-H. Byun, and M. Shur, "A unified current-voltage model for long-channel nMOSFETs," Solid State Commun., vol. 38, no. 2, pp. 399-406, 1991.
8. R. Howes, W. Redman-White, K. Nichols, P. Mole, M. Robinson, and S. Bird, "An SOS MOSFET model based on calculation of the surface potential," IEEE Trans. Computer-Aided Des. Integr. Circuits Syst., vol. 13, no. 4, pp. 494-506, Apr. 1994.
9. A. I. A. Cunha, M. C. Schneider, and C. Galup-Montoro, "An MOS transistor model for analog circuit design," IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, Oct. 1998.
10. H. K. Gummel and K. Singhal, "Inversion charge modeling," IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 1585-1593, Aug. 2001.
11. B. Iniguez, L. Ferreira, B. Gentinne, and D. Flandre, "A physically-based C∞-continuous fully-depleted SOI MOSFET model for analog applications," IEEE Trans. Electron Devices, vol. 43, no. 4, pp. 568-575, Apr. 1996.
12. G. Baccarani and S. Reggiani, "A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects," IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1656-1666, Aug. 1999.
13. L. Ge, J. G. Possum, and B. Liu, "Physical compact modeling and analysis of velocity overshoot in extremely scaled CMOS devices and circuits," IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2074-2080, Sep. 2001.
14. M. Buttiker, "Role of quantum coherence in series resistors," Phys. Rev. B, Condens. Matter, no. 33, pp. 3020-3026, 1986.
15. S. Datta, "Nanoscale device modeling: The Green's function method," Superlatt. Microstruct., vol. 28, no. 4, pp. 253-278, Oct. 2000.
16. J. Lopez-Villanueva, P. Cartujo-Cassinello, F. Gamiz, J. Banqueri, and A. Palma, "Effects of the inversion layer centroid on the performance of double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 141-146, Jan. 2000.
17. C. R. Crowell and M. Hafizi, "Current transport over parabolic potential barriers in semiconductor devices," IEEE Trans. Electron Devices, vol. 35, no. 7, pp. 1087-1095, Jul. 1988.
18. R. M. Corless and D. J. Jeffrey, "The Wright ω function," in Proc. Int. Conf. Artificial Intelligence, Automated Reasoning, Symbolic Computation, 2002, pp. 76-89.
19. R. Lipperheide, T. Weis, and U. Wille, "Generalized drude model: Unification of ballistic and diffusive electron transport," Phys. Rev. B, Condens. Matter, no. 13, pp. 3347-3363, Apr. 2001.
20. G. Gildenblat, "One-flux theory of a nonabsorbing barrier," J. Appl. Phys., vol. 91, no. 12, pp. 9883-9886, Jun. 2002.
21. H. Wang and G. Gildenblat, "Scattering matrix based compact MOSFET model," in IEDM Tech. Dig., Dec. 2002, pp. 125-128.
22. Z. Ren and M. Lundstrom, "Simulation of nanoscale MOSFETs: A scattering theory interpretation," Superlatt. Microstruct., vol. 27, no. 2-3, pp. 177-189, Feb. 2000.
23. A. Rahman and M. Lundstrom, "A compact scattering model for the nanoscale double-gate MOSFET," IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 481-489, Mar. 2002.
24. D. Caughey and R. Thomas, "Carrier mobilities in silicon empirically related to doping and field," Proc. IEEE, vol. 55, no. 12, pp. 2192-2193, Dec. 1967.
25. V. K. Arora, "Drift diffusion and einstein relation for electrons in silicon sujected to a high electric field," Appl. Phys. Lett., vol. 80, no. 20, pp. 3763-3765, May 2002.
26. "Quantum engineering of nanoeletronic devices: The role of quantum emission in limiting drift velocity and diffusion coefficient," Microelectron. J., vol. 80, no. 31, pp. 853-859, 2000.
27. S. Zukotynski and W. Howlett, "Carrier distribution function in semiconductors," Solid State Electron., vol. 21, no. 1, pp. 35-41, Jan. 1978.
28. W. R. Bandy and R. S. Winton, "A new approach for modeling the MOSFET using a simple, continuous analytical expression for drain conductance which includes velocity-saturation in a fundamental way," IEEE Trans. Computer-Aided Des. Integr. Circuits Syst., vol. 15, no. 5, pp. 475-483, May 1996.
29. M. A. Maher and C. Mead, "A physical charge-controlled model for MOS transistors," in Advanced Research in VLSI, P. Losleben, Ed. Cambridge, MA: MIT Press, 1987.
30. K. Joardar, K. Gulallapalli, C. McAndrew, M. Burnham, and A. Wild, "An improved MOSFET model for circuit simulation," IEEE Trans. Electron Devices, vol. 45, no. 1, pp. 134-148, Jan. 1998.
31. J. Wang and M. Lundstrom, "Ballistic transport in high electron mobility transistors," IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1604-1609, Jul. 2003.
32. J.-M. Sallese, M. Bucher, and C. Lallement, "Improved analytical modeling of polysilicon depletion in MOSFETs for circuit simulation," Solid State Electron., vol. 44, pp. 905-912, Jun. 2000.
33. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., Dec. 2002, pp. 251-254.
34. K. Natori, "Ballistic metal-oxide-semiconductor field effect transistor," J. Appl. Phys., vol. 75, no. 8, pp. 4879-4890, Oct. 1994.