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Volumn , Issue , 2003, Pages 376-381

An effective capacitance based driver output model for on-chip RLC interconnects

Author keywords

Design; Performance

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC LINES; INTERCONNECTION NETWORKS;

EID: 0043136706     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775832.775931     Document Type: Conference Paper
Times cited : (20)

References (11)
  • 3
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    • Performance computation for pre-characterized CMOS gates with RC loads
    • May
    • F. Dartu, N. Menezes, and L.T. Pileggi, "Performance computation for pre-characterized CMOS gates with RC loads," IEEE Trans. CAD, 15, (May 1996), pp. 544-553.
    • (1996) IEEE Trans. CAD , vol.15 , pp. 544-553
    • Dartu, F.1    Menezes, N.2    Pileggi, L.T.3
  • 4
    • 0031246188 scopus 로고    scopus 로고
    • When are transmission line effects important for on-chip interconnections?
    • Oct.
    • A. Deutsch et al., "When are transmission line effects important for on-chip interconnections?" IEEE Trans. on Microwave Theory and Techniques, 45, (Oct. 1997), 1836-1846.
    • (1997) IEEE Trans. on Microwave Theory and Techniques , vol.45 , pp. 1836-1846
    • Deutsch, A.1
  • 5
    • 0031643950 scopus 로고    scopus 로고
    • Performance criteria for evaluating the importance of on-chip inductance
    • Y. Ismail, E. Friedman, and J. Neves, "Performance criteria for evaluating the importance of on-chip inductance," Int. Symp. Circuits and Systems, 1998, pp. 244-247.
    • (1998) Int. Symp. Circuits and Systems , pp. 244-247
    • Ismail, Y.1    Friedman, E.2    Neves, J.3
  • 6
    • 0033725695 scopus 로고    scopus 로고
    • A realizable driving point model for on-chip interconnect with inductance
    • C.V. Kashyap and B.L. Krauter, "A realizable driving point model for on-chip interconnect with inductance," Design Automation Conference, 2000, pp. 190-195.
    • (2000) Design Automation Conference , pp. 190-195
    • Kashyap, C.V.1    Krauter, B.L.2
  • 9
    • 0024906813 scopus 로고
    • Modeling the driving point characteristic of resistive interconnect for accurate delay estimation
    • P.R. O'Brien and T.L. Savarino, "Modeling the driving point characteristic of resistive interconnect for accurate delay estimation," Int. Conf. Computer Aided Design, 1989, pp. 512-515.
    • (1989) Int. Conf. Computer Aided Design , pp. 512-515
    • O'Brien, P.R.1    Savarino, T.L.2
  • 10
    • 0025414182 scopus 로고
    • Asymptotic waveform evaluation for timing analysis
    • April
    • L.T. Pillage and R. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. CAD, 9, (April 1990), pp. 352-366.
    • (1990) IEEE Trans. CAD , vol.9 , pp. 352-366
    • Pillage, L.T.1    Rohrer, R.2
  • 11
    • 0028756124 scopus 로고
    • Modeling the effective capacitance for the RC interconnect of CMOS gates
    • Dec
    • J. Qian, S. Pullela, and L.T. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. CAD, 13, (Dec 1994), pp. 1526-1535.
    • (1994) IEEE Trans. CAD , vol.13 , pp. 1526-1535
    • Qian, J.1    Pullela, S.2    Pillage, L.T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.