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Volumn , Issue , 2003, Pages 776-781

Architecting ASIC libraries and flows in nanometer era

Author keywords

Libraries; Nanometer design; Standard Cell

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL LIBRARIES; MICROPROCESSOR CHIPS; NANOTECHNOLOGY;

EID: 0042134646     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775832.776030     Document Type: Conference Paper
Times cited : (19)

References (10)
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    • Increase in the random dopant induced threshold fluctuations and lowering in sub-100nm mosfets
    • Apr
    • Asenov et al. Increase in the Random Dopant Induced Threshold Fluctuations and Lowering in sub-100nm mosfets.... IEEE Trans on Electron Devices Apr 2001
    • (2001) IEEE Trans on Electron Devices
    • Asenov1
  • 3
    • 0037346053 scopus 로고    scopus 로고
    • Process and circuit design interlock for application-dependant scaling tradeoffs and optimization in the SOC era
    • March
    • Diaz C.H. Process and Circuit Design Interlock for Application-Dependant Scaling Tradeoffs and Optimization in the SOC Era. IEEE JSSC (March 2003 vol. 38), 444-449.
    • (2003) IEEE JSSC , vol.38 , pp. 444-449
    • Diaz, C.H.1
  • 5
    • 0041691440 scopus 로고    scopus 로고
    • Practical application of full-feature alternating phase shifting technology for a phase aware std cell design flow
    • Sanie M. et al. Practical Application of Full-Feature Alternating Phase shifting Technology for a Phase aware Std Cell design flow. Proc. DAC 2001.
    • (2001) Proc. DAC
    • Sanie, M.1
  • 6
    • 84948452037 scopus 로고    scopus 로고
    • Statistical methods for the determination of process corners
    • Kocher M and Rappitsch G. Statistical Methods for the Determination of process Corners Proc. ISQED 2002
    • (2002) Proc. ISQED
    • Kocher, M.1    Rappitsch, G.2
  • 7
    • 0042693277 scopus 로고    scopus 로고
    • A statistical STA considering correlations between delays
    • Tsukiyama et al. A statistical STA considering correlations between delays. Proc DAC 2001
    • (2001) Proc DAC
    • Tsukiyama1
  • 8
    • 0027614893 scopus 로고
    • Statistical timing analysis of combinatorial logic circuits
    • H.F. Jyu, Malik S et al. Statistical timing analysis of combinatorial logic circuits IEEE trans. VLSI Systems vol. 1, no 2 1993
    • (1993) IEEE Trans. VLSI Systems , vol.1 , Issue.2
    • Jyu, H.F.1    Malik, S.2
  • 9
    • 0033280060 scopus 로고    scopus 로고
    • The impact of bias temperature instability
    • N. Kimizuka et. al. "The Impact of Bias temperature instability ..." Symposium on VLSI technology 1999, 73-74
    • (1999) Symposium on VLSI Technology , pp. 73-74
    • Kimizuka, N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.