Hybrid PPC methodology using multi-step correction and implementation for the sub-100nm node

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5040 II, Issue , 2003, Pages 1176-1183

  Choi, Soo Han ^a   Park, Ji Soong ^a   Park, Chul Hong ^a   Chung, Won Young ^a   Kim, In Sung ^a   Kim, Dong Hyun ^a   Kim, Yoo Hyon ^a   Yoo, Moon Hyun ^a   Kong, Jeong Taek ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

ACLV; Empirical model; Hybrid PPC; Multi step correction; Process window; Sub resolution assist feature

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MICROPROCESSOR CHIPS; OPTIMIZATION;

ACROSS-CHIP LINE-WIDTH VARIATION; EMPIRICAL MODEL; MULTI-STEP CORRECTION; PROCESS PROXIMITY CORRECTION; PROCESS WINDOW; SUB-RESOLUTION ASSIST FEATURE;

LITHOGRAPHY;

EID: 0141721828     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.485397     Document Type: Conference Paper

References (7)

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3. Allen Gabor, et al., "Sub-resolution assist feature implementation for high performance logic gate-level lithography", in Proc. SPIE, vol. 4691, pp. 418-425, 2002
4. K. Hashimoto, et al., "Tandem process proximity correction method", in Proc. SPIE, vol. 4691, pp. 1070-1081, 2002
5. W. Y. Chung, et al., "Profile and equipment simulation for the self-aligned contact etch process by C4F8 plasmas", Dry Process Symposium (DPS), 2001
6. J. F. Chen, et al., "Optical proximity correction method for intermediate-pitch features using sub-resolution scattering bars on a mask", US Patent #5821014, 10/13/1998
7. C. H. Park, et al., "Optical proximity correction considering mask manufacturability and its application to 0.25um DRAM for enhanced device performance", in Proc. SPIE, vol. 4000, pp. 1041-1045, 2000