Simulation-based critical area extraction and litho-friendly layout design for low k1 lithography

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5377, Issue PART 2, 2004, Pages 713-720

  Choi, Soo Han ^a   Ban, Yong Chan ^a   Lee, Ki Heung ^a   Kim, Dong Hyun ^a   Hong, Ji Suk ^a   Kim, Yoo Hyon ^a   Yoo, Moon Hyun ^a   Kong, Jeong Taek ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Critical area extraction; Layout editor environment; Litho friendly layout; Optical proximity correction; Process margin; Selective simulation

Indexed keywords

AUTOMATION; COMPUTER SIMULATION; ERROR ANALYSIS; IMAGE ANALYSIS; OPTIMIZATION; PROBABILITY DENSITY FUNCTION; SEMICONDUCTOR MATERIALS;

CRITICAL AREA EXTRACTION; LITHO-FRIENDLY LAYOUT; OPTICAL PROXIMITY CORRECTION; PROCESS MARGIN; SELECTIVE SIMULATION;

PHOTOLITHOGRAPHY;

EID: 3843104609     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.535008     Document Type: Conference Paper

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