-
1
-
-
0036049224
-
Integration of high-performance and, low leakage and mixed signal features into a 100 nm CMOS technology
-
T. Schafbauer et al., "Integration of high-performance and, low leakage and mixed signal features into a 100 nm CMOS technology," in Symp. VLSI Technol., Dig. Tech. Papers, 2002, pp. 62-63.
-
Symp. VLSI Technol., Dig. Tech. Papers, 2002
, pp. 62-63
-
-
Schafbauer, T.1
-
2
-
-
0036053622
-
UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect
-
K. Fukasaku et al., "UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect," in Symp. VLSI Technol., Dig. Tech. Papers, 2002, pp. 64-65.
-
Symp. VLSI Technol., Dig. Tech. Papers, 2002
, pp. 64-65
-
-
Fukasaku, K.1
-
3
-
-
0035716657
-
High performance 35 nm gate length CMOS with NO oxinitride gate dielectric and Ni salacide
-
S. Inaba et al., "High performance 35 nm gate length CMOS with NO oxinitride gate dielectric and Ni salacide," in IEDM Tech. Dig., 2001, pp. 641-644.
-
(2001)
IEDM Tech. Dig.
, pp. 641-644
-
-
Inaba, S.1
-
4
-
-
0041537580
-
Transistor elements for 30 nm physical gate length and beyond
-
B. Daoyle et al., "Transistor elements for 30 nm physical gate length and beyond," Intel Technol. J., vol. 6, p. 42, 2002.
-
(2002)
Intel Technol. J.
, vol.6
, pp. 42
-
-
Daoyle, B.1
-
5
-
-
0027813761
-
Three dimensional 'atomistic' simulation of discrete random dopant distribution effects in sub-0.1 μm MOSFETs
-
H.-S. Wong and Y. Taur, "Three dimensional 'atomistic' simulation of discrete random dopant distribution effects in sub-0.1 μm MOSFETs," in IEDM Tech. Dig., 1993, pp. 705-708.
-
(1993)
IEDM Tech. Dig.
, pp. 705-708
-
-
Wong, H.-S.1
Taur, Y.2
-
6
-
-
0032164821
-
Modeling statistical dopant fluctuations in MOS transistors
-
Sept.
-
P. A. Stolk, F. P. Widdershoven, and D. B. M. Klaassen, "Modeling statistical dopant fluctuations in MOS transistors," IEEE Trans. Electron Devices, vol. 45, pp. 1960-1971, Sept. 1998.
-
(1998)
IEEE Trans. Electron Devices
, vol.45
, pp. 1960-1971
-
-
Stolk, P.A.1
Widdershoven, F.P.2
Klaassen, D.B.M.3
-
7
-
-
0032320827
-
Random dopant induced threshold voltage lowering and fluctuations in sub 0.1 micron MOSFETs: A 3D 'atomistic' simulation study
-
Dec.
-
A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub 0.1 micron MOSFETs: A 3D 'atomistic' simulation study," IEEE Trans. Electron Devices, vol. 45, pp. 2505-2513, Dec. 1998.
-
(1998)
IEEE Trans. Electron Devices
, vol.45
, pp. 2505-2513
-
-
Asenov, A.1
-
8
-
-
0033872616
-
Polysilicon gate enhancement of the random dopant induced threshold voltage fluctuations in sub 100 nm MOSFET's with tunnelling oxide
-
Apr.
-
A. Asenov and S. Saini, "Polysilicon gate enhancement of the random dopant induced threshold voltage fluctuations in sub 100 nm MOSFET's with tunnelling oxide," IEEE Trans. Electron Devices, vol. 47, pp. 805-812, Apr. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, pp. 805-812
-
-
Asenov, A.1
Saini, S.2
-
9
-
-
0036247929
-
Intrinsic threshold voltage fluctuations in decananometer MOSFET's due to local oxide thickness variations
-
June
-
A. Asenov, S. Kaya, and J. H. Davies, "Intrinsic threshold voltage fluctuations in decananometer MOSFET's due to local oxide thickness variations," IEEE Trans. Electron Devices, vol. 49, pp. 112-119, June 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, pp. 112-119
-
-
Asenov, A.1
Kaya, S.2
Davies, J.H.3
-
10
-
-
0033714120
-
Modeling line edge roughness effects in sub 100 nm gate length devices
-
P. Oldiges, Q. Lin, K. Pertillo, M. Sanchez, M. Leong, and M. Hargrove, "Modeling line edge roughness effects in sub 100 nm gate length devices," in Proc. SISPAD, 2000, pp. 131-134.
-
Proc. SISPAD, 2000
, pp. 131-134
-
-
Oldiges, P.1
Lin, Q.2
Pertillo, K.3
Sanchez, M.4
Leong, M.5
Hargrove, M.6
-
11
-
-
0003161077
-
Analysis of statistical fluctuations due to line edge roughness in sub 0.1 μm MOSFET's
-
D. Tsoukalas and C. Tsamis, Eds. Vienna, Austria: Springer-Verlag
-
S. Kaya, A. R. Brown, A. Asenov, D. Magot, and T. Linton, "Analysis of statistical fluctuations due to line edge roughness in sub 0.1 μm MOSFET's," in Simulation of Semiconductor Processes and Devices 2001, D. Tsoukalas and C. Tsamis, Eds. Vienna, Austria: Springer-Verlag, 2001, pp. 78-81.
-
(2001)
Simulation of Semiconductor Processes and Devices 2001
, pp. 78-81
-
-
Kaya, S.1
Brown, A.R.2
Asenov, A.3
Magot, D.4
Linton, T.5
-
12
-
-
84890405910
-
The effects of development parameter on the line edge roughness in sub-0.20 μm line patterns
-
H. Taejoong, S. B. Lee, H.-J. Yang, and J. Park, "The effects of development parameter on the line edge roughness in sub-0.20 μm line patterns," in Proc. VLSI and CAD 1999-ICVC '99, 1999, pp. 490-493.
-
Proc. VLSI and CAD 1999-ICVC '99, 1999
, pp. 490-493
-
-
Taejoong, H.1
Lee, S.B.2
Yang, H.-J.3
Park, J.4
-
13
-
-
11744386910
-
Reduction of line edge roughness in the top surface imaging process
-
S. Mori, T. Morisawa, N. Matsuzawa, Y. Kaimoto, M. Endo, T. Matsuo, K. Kuhara, and M. Sasago, "Reduction of line edge roughness in the top surface imaging process," J. Vac. Sci. Tech. B, vol. 16, pp. 3739-3743, 1998.
-
(1998)
J. Vac. Sci. Tech. B
, vol.16
, pp. 3739-3743
-
-
Mori, S.1
Morisawa, T.2
Matsuzawa, N.3
Kaimoto, Y.4
Endo, M.5
Matsuo, T.6
Kuhara, K.7
Sasago, M.8
-
14
-
-
0042939743
-
Metrology method for the correlation of line edge roughness for different resists before and after etch
-
S. Winkelmeier, M. Sarstedt, M. Ereken, M. Goethals, and K. Ronse, "Metrology method for the correlation of line edge roughness for different resists before and after etch," Microelec. Eng., vol. 665, pp. 57-58, 2001.
-
(2001)
Microelec. Eng.
, vol.665
, pp. 57-58
-
-
Winkelmeier, S.1
Sarstedt, M.2
Ereken, M.3
Goethals, M.4
Ronse, K.5
-
15
-
-
0040708648
-
Demonstration of pattern transfer into sub-100 nm polysilicon line/space features patterned with extreme ultraviolet lithography
-
G. F. Cardinale, C. C. Henderson, J. E. M. Goldsmith, P. J. S. Mangat, J. Cobb, and S. D. Hector, "Demonstration of pattern transfer into sub-100 nm polysilicon line/space features patterned with extreme ultraviolet lithography," J. Vac. Sci. Tech. B, vol. 17, pp. 2970-2974, 1999.
-
(1999)
J. Vac. Sci. Tech. B
, vol.17
, pp. 2970-2974
-
-
Cardinale, G.F.1
Henderson, C.C.2
Goldsmith, J.E.M.3
Mangat, P.J.S.4
Cobb, J.5
Hector, S.D.6
-
16
-
-
0033640381
-
Resolution limiting mechanism in electron beam lithography
-
M. Yoshizawa and S. Moriya, "Resolution limiting mechanism in electron beam lithography," Electron. Lett., vol. 36, pp. 90-91, 2000.
-
(2000)
Electron. Lett.
, vol.36
, pp. 90-91
-
-
Yoshizawa, M.1
Moriya, S.2
-
17
-
-
0029732738
-
Sub-35 nm metal gratings fabricated using PMMA with high resolution studies on Hoechst AZ PN 114 chemically amplified resist
-
S. Thoms and D. S. Macintyre, "Sub-35 nm metal gratings fabricated using PMMA with high resolution studies on Hoechst AZ PN 114 chemically amplified resist," Microelectron. Eng., vol. 30, pp. 327-330, 1996.
-
(1996)
Microelectron. Eng.
, vol.30
, pp. 327-330
-
-
Thoms, S.1
Macintyre, D.S.2
-
18
-
-
0035364688
-
An experimentally validated analytical model for gate line edge roughness (LER) effects on technology scaling
-
June
-
C. H. Diaz, H.-J. Tao, Y.-C. Ku, A. Yen, and K. Young, "An experimentally validated analytical model for gate line edge roughness (LER) effects on technology scaling," IEEE Electron Device Lett., vol. 22, pp. 287-289, June 2001.
-
(2001)
IEEE Electron Device Lett.
, vol.22
, pp. 287-289
-
-
Diaz, C.H.1
Tao, H.-J.2
Ku, Y.-C.3
Yen, A.4
Young, K.5
-
19
-
-
0002431386
-
The impact of line edge roughness on 100 nm device performance
-
T. Linton, M. Giles, and P. Packan, "The impact of line edge roughness on 100 nm device performance," in Ext. Abs. Silicon Nanoelectronics Workshop, 1998, pp. 82-83.
-
Ext. Abs. Silicon Nanoelectronics Workshop, 1998
, pp. 82-83
-
-
Linton, T.1
Giles, M.2
Packan, P.3
-
20
-
-
0035695567
-
3D modeling of fluctuation effects in heavily scaled VLSI devices
-
T. D. Linton, S. Yu, and R. Shaheed, "3D modeling of fluctuation effects in heavily scaled VLSI devices," VLSI Design, vol. 13, pp. 103-109, 2001.
-
(2001)
VLSI Design
, vol.13
, pp. 103-109
-
-
Linton, T.D.1
Yu, S.2
Shaheed, R.3
-
21
-
-
0012303666
-
Transistor width dependence of LER degradation to CMOS device characteristics
-
J. Wu, J. Chen, and K. Liu, "Transistor width dependence of LER degradation to CMOS device characteristics," in Proc. SISPAD, Kobe, Japan, 2002, pp. 95-98.
-
Proc. SISPAD, Kobe, Japan, 2002
, pp. 95-98
-
-
Wu, J.1
Chen, J.2
Liu, K.3
-
22
-
-
0042038762
-
Modeling and analysis of gate line edge roughness effect on CMOS scaling toward deep nanoscale gate length
-
S.-D. Kim, S. Hong, J.-K. Park, and J. C. S. Woo, "Modeling and analysis of gate line edge roughness effect on CMOS scaling toward deep nanoscale gate length," in Extended Abstr. Int. Conf. Solid State Devices Mater., 2002, pp. 20-21.
-
Extended Abstr. Int. Conf. Solid State Devices Mater., 2002
, pp. 20-21
-
-
Kim, S.-D.1
Hong, S.2
Park, J.-K.3
Woo, J.C.S.4
-
23
-
-
0033312006
-
Hierarchical approach to 'atomistic' 3D MOSFET simulation
-
Nov.
-
A. Asenov, A. R. Brown, J. H. Davies, and S. Saini, "Hierarchical approach to 'atomistic' 3D MOSFET simulation," IEEE Trans. Computer-Aided Des., vol. 18, pp. 1558-1565, Nov. 1999.
-
(1999)
IEEE Trans. Computer-Aided Des.
, vol.18
, pp. 1558-1565
-
-
Asenov, A.1
Brown, A.R.2
Davies, J.H.3
Saini, S.4
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