A hybrid PPC method based on the empirical etch model for the 0.14μm DRAM generation and beyond

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 143-147

  Park, Chul Hong ^a   Choi, Soo Han ^a   Rhie, Sang Uhk ^a   Kim, Dong Hyun ^a   Park, Jun Seong ^a   Jang, Tae Hwang ^a   Park, Ji Soong ^a   Kim, Yoo Hyon ^a   Yoo, Moon Hyun ^a   Kong, Jeong Taek ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Circuits; Error correction; Etching; Hybrid power systems; Lithography; Nearest neighbor searches; Nonlinear distortion; Proximity effect; Random access memory; Very large scale integration

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; ERROR CORRECTION; ETCHING; LITHOGRAPHY; NEAREST NEIGHBOR SEARCH; NETWORKS (CIRCUITS); NONLINEAR DISTORTION; VLSI CIRCUITS;

DEVICE PERFORMANCE; EMPIRICAL MODEL; HYBRID POWER SYSTEMS; MODEL-BASED OPC; PROCESS PROXIMITY CORRECTIONS; PROXIMITY EFFECTS; RANDOM ACCESS MEMORY; YIELD IMPROVEMENT;

RANDOM ACCESS STORAGE;

EID: 9244225036     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996717     Document Type: Conference Paper

References (15)

1. O. W. Otto, et. al., "Automated optical proximity correction - a rule-based approach," SPIE Proc., vol. 2197, pp. 278-293, 1994.
2. J. Stirniman, et. al., "Fast proximity correction with zone sampling," SEMATECH DUV Lithography Workshop, pp. 16-18, 1996.
3. C. H. Park, et. al., "Practical approach to control the full chip level gate CD in DUV lithography," in. SPIE Proc., vol. 3334, pp. 215-223, 1998.
4. J. S. Park, et. al., "An efficient rule-based OPC approach using a DRC tool for 0.18um ASIC," IEEE ISQED, pp. 82-85, 2000.
5. T. Kotani, et. al., "Highly accurate process proximity correction based on empirical model for 0.18um generation and beyond," Jpn. J. Appl. Phys. vol. 38, pp. 6957-6962, 1999.
6. C. H. Park, et. al., "A systematic approach to correct critical patterns induced by the lithography process at the full-chip level," SPIE Proc., vol. 3679, pp. 622-629, 1999.
7. C. H. Park, et. al., "Optical proximity correction considering mask manufacturability and its application to the enhanced performance of 0.25um DRAM," SPIE Proc., vol. 2197, pp. 1041-1046, 2000.
8. Y. Granik, et. al., "Correction for etch proximity : new method and applications," SPIE Proc., vol. 4346, pp.98-p112, 2001.
9. Nick Cobb, et. al., "Experimental results on a optical proximity correction with variable threshold model," SPIE Proc., vol. 3051, pp.458-462, 1997.
10. F. Zach, et. al., "Process dependencies of Optical proximity Corrections," SPIE Proc., vol. 4346, pp.113-118, 2001.
11. A. Misaka, et. al., " A statistical critical dimension control at CMOS cell level", IEDM, pp. 631-634, 1996.
12. J. K. Tyminski, et. al., "CD control of ASIC polysilicon gate level," SPIE Proc., vol. 3334, pp. 607-619, 1998.
13. C. Hedlund, et. al., "Microloading effect in reactive ion etching," J. Vac. Sci. Technol. A, vol.12, no. 4, pp.1962-1965, 1994
14. J. F. Chen, et. al., " Optical proximity correction for inermediate-pitch features using sub-resolution scattering bar," J. Vac. Sci. Technol. B, vol. 15, pp.2426-2433, 1997.
15. L. Liebmann, et. al., " Optical proximity correction : a first look at manufacturability," Microlithography World, vol. 4, no. 2, pp.7-11, 1995.