An MTCMOS design methodology and its application to mobile computing

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 110-115

  Won, Hyo Sig ^a   Kim, Kyo Sun ^a   Jeong, Kwang Ok ^a   Park, Ki Tae ^b   Choi, Kyu Myung ^a   Kong, Jeong Taek ^a  

^a SAMSUNG Electronics   (South Korea)

^b TOHOKU UNIVERSITY   (Japan)

Author keywords

Application software; Circuits; CMOS technology; Computer applications; Design methodology; High performance computing; Leakage current; Mobile computing; Personal digital assistants; Power dissipation

Indexed keywords

APPLICATION PROGRAMS; CMOS INTEGRATED CIRCUITS; COMPUTER APPLICATIONS; DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY DISSIPATION; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT DESIGN; LEAKAGE CURRENTS; LOW POWER ELECTRONICS; MOBILE COMPUTING; NETWORKS (CIRCUITS); POWER ELECTRONICS;

CMOS TECHNOLOGY; DESIGN METHODOLOGY; HIGH PERFORMANCE COMPUTING; ITS APPLICATIONS; LEAKAGE POWER; LOW-POWER DESIGN; MULTI-THRESHOLD CMOS; PERSONAL DIGITAL ASSISTANTS (PDA);

PERSONAL DIGITAL ASSISTANTS;

EID: 1542299299     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231845     Document Type: Conference Paper

References (11)

1. S. Mutoh, et al., "A 1V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application", ISSCC, 1996.
2. T. Kuroda, et al., "A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold Voltage Scheme" ISSCC, 1996.
3. S. Shigematsu, S. Mutoh, et al, "A 1-V high-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits", IEEE Journal of Solid-state Circuits, 1997.
4. H. Makino, et al., T. Shimizu and T. Arakawa, "An Auto-Backgate-Controlled MT-CMOS Circuit", Symp. on VLSI Circuits Digest of Technical Papers, 1998.
5. K. Kumagai, et al., "A Novel Powering-down Scheme for Low Vt CMOS Circuits", Symp. on VLSI Circuits Digest of Technical Papers, 1998.
6. A. Keshavarzi, et al, "Technology scaling behavior of optimum reverse bias for standby leakage power reduction in CMOS IC's", ISLPED, 1999.
7. James Kao, Siva Narendra and Anantha Chandrakasan, "MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns", DAC, 1998.
8. S. Mutoh, et al., "Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs", ASP-DAC, 1999.
9. J.T. Kao and A.P. Chandrakasan, "Dual- Threshold Voltage Techniques for Low-Power Digital Circuits", Journal of Solid-State Circuits, 2000.
10. K.T. Park, H.S. Won et al., "A New Low -Power Edge-Triggered and Logic-Embedded FF Using Complementary Pass-Transistors Circuit", ITC-CSCC, 2001.
11. K.T. Park, H.S. Won et al., "Low-Power Data-Preserving Complementary Pass-Transistor-Based Circuit for Power-Down Circuit Scheme", SSDM, 2001.