Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 169-174

  Mukhopadhyay, Saibal ^a   Raychowdhury, Arijit ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Doping profiles; Leakage; Threshold voltage; Tunneling

Indexed keywords

GATES (TRANSISTOR); LEAKAGE CURRENTS; LOGIC CIRCUITS; QUANTUM ELECTRONICS;

COMPACT CURRENT MODELING;

CMOS INTEGRATED CIRCUITS;

EID: 0042090415     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775832.775877     Document Type: Conference Paper

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