CMOS design near the limit of scaling

IBM Journal of Research and Development

Volumn 46, Issue 2-3, 2002, Pages 213-222

  Taur, Yuan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TUNNELING; MICROPROCESSOR CHIPS; MOSFET DEVICES; SEMICONDUCTOR DOPING; THERMODYNAMICS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

TUNNELING LEAKAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0036508201     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.462.0213     Document Type: Article

References (18)

1. Design of ion-implanted MOSFETs with very small physical dimensions
2. CMOS scaling into the nanometer regime
3. Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's
4. CMOS scaling into the 21st century: 0.1 μm and beyond
5. Device scaling limits of Si MOSFETs and their application dependencies
6. Generalized scale length for two-dimensional effects in MOSFET's
7. 25 nm CMOS design considerations
8. Source-drain extension scaling for 0.1 μm and below channel length MOSFETs
9. On effective channel length in 0.1 μm MOSFETs
10. Monte Carlo modeling of threshold variation due to dopant fluctuations
11. Monte Carlo analysis of semiconductor devices: The DAMOCLES program
12. On universality of inversion-layer mobility in n- and p-channel MOSFETs
13. Very small MOSFETs for low temperature operation
14. CMOS devices below 0.1 μm: How high will performance Go?
15. CMOS scaling beyond 0.1 μm: How far can It go?
16. Modeling of 10-nm-scale ballistic MOSFETs