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Semiconductor memories for IT era
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C. G. Hwang, "Semiconductor memories for IT era," in ISSCC Dig. Tech. Papers, 2002, pp. 24-27.
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Hwang, C.G.1
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0036923461
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Highly manufacturable 90 nm DRAM technology
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Y. K. Park, C. H. Cho, K. H. Lee, B. H. Roh, Y. S. Ahn, S. H. Lee, J. H. Oh, J. G. Lee, D. H. Kwak, S. H. Shin, J. S. Bae, S. B. Kim, J. K. Lee, J. Y. Lee, M. S. Kim, J. W. Lee, D. J. Lee, S. H. Hong, D. I. Bae, Y. S. Chun, S. H. Park, C. J. Yun, and T. Chung, "Highly manufacturable 90 nm DRAM technology," in IEDM Tech. Dig., 2002, pp, 819-822.
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Park, Y.K.1
Cho, C.H.2
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Kwak, D.H.9
Shin, S.H.10
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Lee, D.J.17
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Park, S.H.21
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3
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0141649609
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The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88 nm feature size and beyond
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J. Y. Kim, C. S. Lee, S. E. Kim, I. B. Chung, Y. M. Choi, B. J. Park, J. W. Lee, D. I. Kim, Y. S. Hwang, D. S. Hwang, H. K. Hwang, J. M. Park, D. H. Kim, N. J. Kang, M. H. Cho, M. Y. Jeong, H. J. Kim, J. N. Hau, S. Y. Kim, B. Y. Nam, H. S. Park, S. H. Chung, J. H. Lee, J. S. Park, H. S. Kim, Y. J. Park, and K. Kim, "The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88 nm feature size and beyond," in Symp. VLSI Tech., 2003, pp. 11-12.
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Kim, J.Y.1
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Kim, S.Y.19
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4
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0036927923
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A novel robust TiN/AHO/TiN capacitor and CoSi2 cell pad structure for 70 nm stand-alone und embedded DRAM technology and beyond
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J. M. Park, Y. S. Hwang, D. S. Hwang, H. K. Hwang, S. H. Lee, G. Y. Kim, M. Y. Jeong, B. J. Park, S. E. Kim, M. H. Cho, D. I. Kim, J.-H. Chung, I. S. Park, C.-Y. Yoo, J. H. Lee, B. Y. Nam, Y. R. Park, C.-S. Kim, M.-C. Sun, J.-H. Ku, S. Choi, H. S. Kim, Y. G. Park, und K. Kim, "A novel robust TiN/AHO/TiN capacitor and CoSi2 cell pad structure for 70 nm stand-alone und embedded DRAM technology and beyond," in IEDM Tech. Dig., 2002, pp. 823-826.
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Park, J.M.1
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Hwang, D.S.3
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Nam, B.Y.16
Park, Y.R.17
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5
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0029251968
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A 3.3 V 32 Mb NAND Flash memory with incremental step pulse programming scheme
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K.-D. Suh, B.-H. Suh, Y.-H. Um, J.-K. Kim, Y.-J. Choi, Y.-N. Koh, S.-S. Lee, S.-C. Kwon, B.-S. Choi, J.-S. Yum, J.-H, Choi, J.-R. Kim, and H.-K. Lim, "A 3.3 V 32 Mb NAND Flash memory with incremental step pulse programming scheme," in ISSCC Dig, Tech. Papers. 1995, pp. 128-129.
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Suh, K.-D.1
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Koh, Y.-N.6
Lee, S.-S.7
Kwon, S.-C.8
Choi, B.-S.9
Yum, J.-S.10
Choi, J.-H.11
Kim, J.-R.12
Lim, H.-K.13
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6
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0030081176
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A 3.3 V 128 Mb multi-level SAND Flash memory for mass storage applications
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T.-S. Jung, Y.-J. Choi, K.-D. Suh, B.-H. Suh, J.-K. Kim, Y.-H, Lim, Y.-N. Koh, J.-W. Park, K.-J. Lee, J.-H. Park, K.-T. Park, J.-R. Kim, J.-H. Lee, and H.-K. Lim, "A 3.3 V 128 Mb multi-level SAND Flash memory for mass storage applications," in ISSCC Dig. Tech. Papers, 2001. pp. 32-33,
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Jung, T.-S.1
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Lim, Y.-H.6
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7
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0036931289
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2 cell size using 90 nm Flash technology
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2 cell size using 90 nm Flash technology," in IEDM Tech. Dig., 2002, pp. 919-922.
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Kim, D.-C.1
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Lee, J.-H.5
Hur, S.-H.6
Baik, I.-G.7
Shin, Y.-C.8
Lee, C.-H.9
Yoon, J.-S.10
Lee, H.-G.11
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Choi, S.-W.13
You, B.-K.14
Choi, J.-H.15
Park, D.16
Kim, K.17
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8
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0038306352
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A 1.8 V 2-Gb NAND Flash memory for mass storage application
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J. Lee, S.-S. Lee, O.-S. Kown, K.-H. Lee, K.-H. Lee, D.-S. Byeon, I.-Y. Kim, Y.-H. Lim, B.-S. Choi, J.-S. Lee, W.-C. Shin, J.-H. Choi, and K.-D. Suh, "A 1.8 V 2-Gb NAND Flash memory for mass storage application," in ISSCC Dig. Tech. Papers, 2003, pp. 290-291.
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Lee, J.1
Lee, S.-S.2
Kown, O.-S.3
Lee, K.-H.4
Lee, K.-H.5
Byeon, D.-S.6
Kim, I.-Y.7
Lim, Y.-H.8
Choi, B.-S.9
Lee, J.-S.10
Shin, W.-C.11
Choi, J.-H.12
Suh, K.-D.13
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