메뉴 건너뛰기




Volumn 44, Issue 3, 2000, Pages 369-378

Future of CMOS technology

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LITHOGRAPHY; TECHNOLOGICAL FORECASTING;

EID: 0033723263     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.443.0369     Document Type: Article
Times cited : (64)

References (11)
  • 2
    • 0000793139 scopus 로고
    • Cramming more components onto integrated circuits
    • April 19
    • Gordon E. Moore, "Cramming More Components onto Integrated Circuits," Electron. 38, 114-117 (April 19, 1965).
    • (1965) Electron. , vol.38 , pp. 114-117
    • Moore, G.E.1
  • 5
    • 4143100441 scopus 로고    scopus 로고
    • Scattering with angular limitation projection electron beam lithography for suboptical lithography
    • November/December
    • Lloyd R. Harriott, "Scattering with Angular Limitation Projection Electron Beam Lithography for Suboptical Lithography," J. Vac. Sci. Technol. B 15, No. 6, 2130-2135 (November/December 1997).
    • (1997) J. Vac. Sci. Technol. B , vol.15 , Issue.6 , pp. 2130-2135
    • Harriott, L.R.1
  • 9
    • 0030291849 scopus 로고    scopus 로고
    • Gigascale integration: Is the sky the limit?
    • November
    • J. D. Meindl, "Gigascale Integration: Is the Sky the Limit?" IEEE Circuits & Devices 12, 19 (November 1996).
    • (1996) IEEE Circuits & Devices , vol.12 , pp. 19
    • Meindl, J.D.1
  • 11
    • 0033689943 scopus 로고    scopus 로고
    • The future of interconnection technology
    • this issue
    • T. N. Theis, "The Future of Interconnection Technology," IBM J. Res. Develop. 44, No. 3, 379-390 (2000, this issue).
    • (2000) IBM J. Res. Develop. , vol.44 , Issue.3 , pp. 379-390
    • Theis, T.N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.