Simulation methodology for assessing the impact of spatial/pattern dependent interconnect parameter variation on circuit performance

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1997, Pages 133-136

  Stine, Brian E ^a   Mehrotra, Vikas ^a   Boning, Duane S ^a   Chung, James E ^a   Ciplickas, Dennis J ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERCONNECT PATTERN DEPENDENT VARIATION;

CAPACITANCE; COMPUTER AIDED DESIGN; COMPUTER SIMULATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 84886448120     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)