메뉴 건너뛰기




Volumn 47, Issue 2-3, 2003, Pages 283-296

Low-power circuits and technology for wireless digital systems

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; MOSFET DEVICES; THRESHOLD VOLTAGE;

EID: 0037686711     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.472.0283     Document Type: Review
Times cited : (26)

References (25)
  • 1
    • 0036507826 scopus 로고    scopus 로고
    • Maintaining the benefits of CMOS scaling when scaling bogs down
    • March/May
    • E. J. Nowak, "Maintaining the Benefits of CMOS Scaling When Scaling Bogs Down," IBM J. Res. & Dev. 46, No. 2/3, 169-180 (March/May 2002).
    • (2002) IBM J. Res. & Dev. , vol.46 , Issue.2-3 , pp. 169-180
    • Nowak, E.J.1
  • 6
    • 0034230287 scopus 로고    scopus 로고
    • Dual-threshold voltage techniques for low-power digital circuits
    • July
    • J. T. Kao and A. P. Chandrakasan, "Dual-Threshold Voltage Techniques for Low-Power Digital Circuits," IEEE J. Solid-State Circuits 35, No. 7, 1009-1018 (July 2000).
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.7 , pp. 1009-1018
    • Kao, J.T.1    Chandrakasan, A.P.2
  • 7
    • 0033707590 scopus 로고    scopus 로고
    • A comparison of dual-rail pass transistor logic families in 1.5V, 1.8μm CMOS technology for low power applications
    • March
    • G. D. Gristede and W. Hwang, "A Comparison of Dual-Rail Pass Transistor Logic Families in 1.5V, 1.8μm CMOS Technology for Low Power Applications," Proceedings of the 2000 Great Lakes Symposium on VLSI, March 2000, pp. 101-106.
    • (2000) Proceedings of the 2000 Great Lakes Symposium on VLSI , pp. 101-106
    • Gristede, G.D.1    Hwang, W.2
  • 9
    • 0029520010 scopus 로고
    • Back gated CMOS on SOIAS for dynamic threshold control
    • December
    • I. Yang, C. Vieri, A. Chandrakasan, and D. Antoniadis, "Back Gated CMOS on SOIAS for Dynamic Threshold Control," IEDM Tech. Digest, pp. 877-880 (December 1995).
    • (1995) IEDM Tech. Digest , pp. 877-880
    • Yang, I.1    Vieri, C.2    Chandrakasan, A.3    Antoniadis, D.4
  • 10
    • 0029359285 scopus 로고
    • 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
    • August
    • S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS," IEEE J, Solid-State Circuits 30, No. 8, 847-854 (August 1995).
    • (1995) IEEE J, Solid-State Circuits , vol.30 , Issue.8 , pp. 847-854
    • Mutoh, S.1    Douseki, T.2    Matsuya, Y.3    Aoki, T.4    Shigematsu, S.5    Yamada, J.6
  • 13
    • 0033116422 scopus 로고    scopus 로고
    • Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
    • April
    • V. Stojanovic and V. Oklobdzija, "Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems," IEEE J. Solid-State Circuits 34, No. 4, 536-548 (April 1999).
    • (1999) IEEE J. Solid-State Circuits , vol.34 , Issue.4 , pp. 536-548
    • Stojanovic, V.1    Oklobdzija, V.2
  • 17
    • 0342778397 scopus 로고    scopus 로고
    • Latches and flip-flops for low power systems
    • A. P. Chandrakasan and R. W. Brodersen, IEEE Press, New York
    • C. Svensson and J. Yuan, "Latches and Flip-Flops for Low Power Systems," in A. P. Chandrakasan and R. W. Brodersen, Low-Power CMOS Design, IEEE Press, New York, 1998, pp. 233-238.
    • (1998) Low-Power CMOS Design , pp. 233-238
    • Svensson, C.1    Yuan, J.2
  • 19
    • 0031162017 scopus 로고    scopus 로고
    • A 1-V high-speed MTCMOS circuit scheme for power-down application circuits
    • June
    • S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits," IEEE J. Solid-State Circuits 32, No. 6, 861-869 (June 1997).
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.6 , pp. 861-869
    • Shigematsu, S.1    Mutoh, S.2    Matsuya, Y.3    Tanabe, Y.4    Yamada, J.5
  • 22
    • 0033722287 scopus 로고    scopus 로고
    • A minimum total power methodology for projecting limits on CMOS GSI
    • June
    • A. Bhavnagarwala, B. Austin, K. Bowman, and J. Meindl, "A Minimum Total Power Methodology for Projecting Limits on CMOS GSI," IEEE Trans. VLSI Syst. 8, No. 3, 235-251 (June 2000).
    • (2000) IEEE Trans. VLSI Syst. , vol.8 , Issue.3 , pp. 235-251
    • Bhavnagarwala, A.1    Austin, B.2    Bowman, K.3    Meindl, J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.