Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 3, 2003, Pages 444-449

  Diaz, Carlos H ^a   Chang, Mi Chang ^a   Ong, Tong Chern ^a   Sun, Jack Yuan Chen ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT DENSITY; DIELECTRIC MATERIALS; ELECTRON TUNNELING; GATES (TRANSISTOR); LEAKAGE CURRENTS; OPTIMIZATION;

APPLICATION-DEPENDENT SCALING TRADEOFFS; CIRCUIT DESIGN INTERLOCK; SILICON ON CHIPS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037346053     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.808318     Document Type: Article

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