Ultra low-leakage power strategies for sub-1 v VLSI: Novel circuit styles and design methodologies for partially depleted silicon-on-insulator (PD-SOI) CMOS technology

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 291-296

  Das, Koushik K ^a   Brown, Richard B ^a  

^a University of Michigan   (United States)

Author keywords

CMOS technology; Design methodology; Leakage current; MOS devices; MOSFET circuits; Silicon on insulator technology; Subthreshold current; Switches; Threshold voltage; Very large scale integration

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT DESIGN; LEAKAGE CURRENTS; MOS DEVICES; MOSFET DEVICES; SEMICONDUCTING SILICON; SWITCHES; SYSTEMS ANALYSIS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

CMOS TECHNOLOGY; DESIGN METHODOLOGY; EFFICIENT IMPLEMENTATION; MOSFET CIRCUITS; PARTIALLY DEPLETED SILICON ON INSULATORS; SUB-THRESHOLD CURRENT; THREE ORDERS OF MAGNITUDE; ULTRA LOW LEAKAGES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 4344597132     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183152     Document Type: Conference Paper

References (10)

1. Shin'ichiro Mutoh, et. al., "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS," IEEE Journal of Solid-State Circuits (JSSC), August 1995, pp. 847-854.
2. Tadahiro Kuroda, et. al., "A 0.9V, 150-MHz, 10-mW, 4mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme," IEEE JSSC, November 1996, pp. 1770-1779.
3. Hiroshi Kawaguchi, et. al., "A Super Cut-off CMOS (SCC-MOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current," IEEE JSSC, Vol. 35, No. 10, Oct. 2000, pp. 1498-1501.
4. M. R. Casu, et. al., "Synthesis of Low-Leakage PD-SOI Circuits with Body-Biasing," ISLPED 2001, pp. 287-290.
5. James T. Kao and Anantha Chandrakasan, "Dual Threshold Voltage Techniques for Low-Power Digital Circuits," IEEE JSSC, Vol. 35, No. 7, July 2000, pp. 1009-1018.
6. Koji Fujii, Takakuni Douseki and Yuichi Kado, "A Sub-1V Dual-Threshold Domino Circuit Using Product-of-Sum Logic," ISLPED 2001, pp. 259-262.
7. James T. Kao, Anantha Chandrakasan and Dimitri Antoniadis, "Transistor Sizing Issues and Tool for Multi-Threshold CMOS Technology," DAC 1997, pp. 409-414.
8. Siva Narendra, et. al., "Scaling of Stack Effect and its Application for Leakage Reduction," ISLPED 2001, pp. 195-200.
9. S. Mutoh, et. al., "Design Method of MTCMOS Power Switch for Low-Voltage High Speed LSIs," ASP-DAC 1999, pp. 113-116.
10. K. K. Das and Richard B. Brown, "A Novel Sub-1 V High Speed Circuit Design Technique in Partially Depleted SOI-CMOS Technology with Ultra Low-Leakage Power," ESS-CIRC 2002, pp. 267-270.