-
4
-
-
84976514297
-
Optimal cache partition-sharing
-
Jacob Brock, Chencheng Ye, Chen Ding, Yechen Li, Xiaolin Wang, and Yingwei Luo. 2015. Optimal cache partition-sharing. In Proceedings of the International Conference on Parallel Processing (ICPP'15). 749- 758.
-
(2015)
Proceedings of the International Conference on Parallel Processing (ICPP'15)
, pp. 749-758
-
-
Brock, J.1
Ye, C.2
Ding, C.3
Li, Y.4
Wang, X.5
Luo, Y.6
-
8
-
-
77951200277
-
Cache hierarchy and memory subsystem of the AMD opteron processor
-
2010
-
Pat Conway, Nathan Kalyanasundharam, Gregg Donley, Kevin Lepak, and Bill Hughes. 2010. Cache hierarchy and memory subsystem of the AMD opteron processor. IEEE Micro. 30, 2 (2010), 16-29.
-
(2010)
IEEE Micro.
, vol.30
, Issue.2
, pp. 16-29
-
-
Conway, P.1
Kalyanasundharam, N.2
Donley, G.3
Lepak, K.4
Hughes, B.5
-
9
-
-
84881160871
-
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
-
Henry Cook, Miquel Moreto, Sarah Bird, Khanh Dao, David A. Patterson, and Krste Asanovic. 2013. A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness. In Proceedings of the International Symposium on Computer Architecture (ISCA'13). 308-319.
-
(2013)
Proceedings of the International Symposium on Computer Architecture (ISCA'13)
, pp. 308-319
-
-
Cook, H.1
Moreto, M.2
Bird, S.3
Dao, K.4
Patterson, D.A.5
Asanovic, K.6
-
10
-
-
84903162429
-
A swap-based cache set index scheme to leverage both superpage and page coloring optimizations
-
Zehan Cui, Licheng Chen, Yungang Bao, and Mingyu Chen. 2014. A swap-based cache set index scheme to leverage both superpage and page coloring optimizations. In Proceedings of the Design Automation Conference. 1-6.
-
(2014)
Proceedings of the Design Automation Conference
, pp. 1-6
-
-
Cui, Z.1
Chen, L.2
Bao, Y.3
Chen, M.4
-
11
-
-
84876561848
-
Improving cache management policies using dynamic reuse distances
-
Nam Duong, Dali Zhao, Taesu Kim, Rosario Cammarota,Mateo Valero, and Alexander V. Veidenbaum. 2012. Improving cache management policies using dynamic reuse distances. In Proceedings of the International Symposium on Microarchitecture. 389-400.
-
(2012)
Proceedings of the International Symposium on Microarchitecture
, pp. 389-400
-
-
Duong, N.1
Zhao, D.2
Kim, T.3
Cammarota, R.4
Valero, M.5
Veidenbaum, A.V.6
-
15
-
-
84857846199
-
The gradient-based cache partitioning algorithm
-
2012
-
William Hasenplaugh, Pritpal S. Ahuja, Aamer Jaleel, Simon Steely Jr., and Joel Emer. 2012. The gradient-based cache partitioning algorithm. ACM Trans. Architect. Code Optim. (TACO) 8, 4 (2012), 44.
-
(2012)
ACM Trans. Architect. Code Optim. (TACO)
, vol.8
, Issue.4
, pp. 44
-
-
Hasenplaugh, W.1
Ahuja, P.S.2
Jaleel, A.3
Steely, S.4
Emer, J.5
-
16
-
-
84965064941
-
Cache QoS: From concept to reality in the Intel Xeon processor E5-2600 v3 product family
-
Andrew Herdrich, Edwin Verplanke, Priya Autee, Ramesh Illikkal, Chris Gianos, Ronak Singhal, and Ravi Iyer. 2016. Cache QoS: From concept to reality in the Intel Xeon processor E5-2600 v3 product family. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA'16). 657-668.
-
(2016)
Proceedings of the International Symposium on High Performance Computer Architecture (HPCA'16)
, pp. 657-668
-
-
Herdrich, A.1
Verplanke, E.2
Autee, P.3
Illikkal, R.4
Gianos, C.5
Singhal, R.6
Iyer, R.7
-
18
-
-
34247143442
-
Communist, utilitarian, and capitalist cache policies on CMPs: Caches as a shared resource
-
Lisa R. Hsu, Steven K. Reinhardt, Ravishankar Iyer, and Srihari Makineni. 2006. Communist, utilitarian, and capitalist cache policies on CMPs: Caches as a shared resource. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'06). 13-22.
-
(2006)
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'06)
, pp. 13-22
-
-
Hsu, L.R.1
Reinhardt, S.K.2
Iyer, R.3
Makineni, S.4
-
20
-
-
36349002905
-
QoS policies and architecture for cache/memory in CMPplatforms
-
2007
-
Ravi Iyer, Li Zhao, Fei Guo, Ramesh Illikkal, SrihariMakineni, Don Newell, Yan Solihin, LisaHsu, and Steve Reinhardt. 2007. QoS policies and architecture for cache/memory in CMPplatforms. ACMSIGMETRICS Perform. Eval. Rev. 35, 1 (2007), 25-36.
-
(2007)
ACMSIGMETRICS Perform. Eval. Rev.
, vol.35
, Issue.1
, pp. 25-36
-
-
Iyer, R.1
Zhao, L.2
Guo, F.3
Illikkal, R.4
SrihariMakineni5
Newell, D.6
Solihin, Y.7
LisaHsu8
Reinhardt, S.9
-
21
-
-
63549149925
-
Adaptive insertion policies for managing shared caches
-
Aamer Jaleel, William Hasenplaugh, Moinuddin Qureshi, Julien Sebot, Simon Steely Jr., and Joel Emer. 2008. Adaptive insertion policies for managing shared caches. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'08). 208-219.
-
(2008)
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT'08)
, pp. 208-219
-
-
Jaleel, A.1
Hasenplaugh, W.2
Qureshi, M.3
Sebot, J.4
Steely, S.5
Emer, J.6
-
22
-
-
70449497716
-
A simple cache partitioning approach in a virtualized environment
-
Xinxin Jin, Haogang Chen, Xiaolin Wang, Zhenlin Wang, Xiang Wen, Yingwei Luo, and Xiaoming Li. 2009. A simple cache partitioning approach in a virtualized environment. In Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA'09). 519- 524.
-
(2009)
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA'09)
, pp. 519-524
-
-
Jin, X.1
Chen, H.2
Wang, X.3
Wang, Z.4
Wen, X.5
Luo, Y.6
Li, X.7
-
26
-
-
84897133868
-
Cache friendliness-aware managementof shared last-level caches for high performance multi-core systems
-
2014
-
Dimitris Kaseridis, Muhammad Faisal Iqbal, and Lizy Kurian John. 2014. Cache friendliness-aware managementof shared last-level caches for high performance multi-core systems. IEEE Trans. Comput. 63, 4 (2014), 874-887.
-
(2014)
IEEE Trans. Comput.
, vol.63
, Issue.4
, pp. 874-887
-
-
Kaseridis, D.1
Faisal Iqbal, M.2
Kurian John, L.3
-
33
-
-
79955093931
-
Power-aware dynamic cache partitioning for CMPs
-
(2011)
-
I. Kotera, K. Abe, R. Egawa, H. Takizawa, and H. Kobayashi. 2011. Power-aware dynamic cache partitioning for CMPs. Trans. HiPEAC (2011), 135-153.
-
(2011)
Trans. HiPEAC
, pp. 135-153
-
-
Kotera, I.1
Abe, K.2
Egawa, R.3
Takizawa, H.4
Kobayashi, H.5
-
34
-
-
84903209395
-
Variation aware cache partitioning for multithreaded programs
-
Vivek Kozhikkottu, Abhisek Pan, Vijay Pai, Sujit Dey, and Anand Raghunathan. 2014. Variation aware cache partitioning for multithreaded programs. In Proceedings of the Design Automation Conference. 1-6.
-
(2014)
Proceedings of the Design Automation Conference
, pp. 1-6
-
-
Kozhikkottu, V.1
Pan, A.2
Pai, V.3
Dey, S.4
Raghunathan, A.5
-
37
-
-
57749186047
-
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
-
J. Lin, Q. Lu, X. Ding, Z. Zhang, X. Zhang, and P. Sadayappan. 2008. Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA'08). 367-378.
-
(2008)
Proceedings of the International Symposium on High Performance Computer Architecture (HPCA'08)
, pp. 367-378
-
-
Lin, J.1
Lu, Q.2
Ding, X.3
Zhang, Z.4
Zhang, X.5
Sadayappan, P.6
-
38
-
-
85019887327
-
Enabling software multicore cache management with lightweight hardware support
-
J. Lin, Q. Lu, X. Ding, Z. Zhang, X. Zhang, and P. Sadayappan. 2009. Enabling software multicore cache management with lightweight hardware support. In Proceedings of the Conference on Supercomputing (SC).
-
(2009)
Proceedings of the Conference on Supercomputing (SC)
-
-
Lin, J.1
Lu, Q.2
Ding, X.3
Zhang, Z.4
Zhang, X.5
Sadayappan, P.6
-
41
-
-
84905453978
-
Going vertical inmemory management: Handling multiplicity by multi-policy
-
Lei Liu, Yong Li, Zehan Cui, Yungang Bao, Mingyu Chen, and ChengyongWu. 2014. Going vertical inmemory management: Handling multiplicity by multi-policy. In Proceedings of the International Symposium on Computer Architecture (ISCA'14). 169-180.
-
(2014)
Proceedings of the International Symposium on Computer Architecture (ISCA'14)
, pp. 169-180
-
-
Liu, L.1
Li, Y.2
Cui, Z.3
Bao, Y.4
Chen, M.5
ChengyongWu6
-
42
-
-
84970021948
-
Improving resource efficiency at scale with heracles
-
2016
-
David Lo, Liqun Cheng, Rama Govindaraju, Parthasarathy Ranganathan, and Christos Kozyrakis. 2016. Improving resource efficiency at scale with heracles. ACM Trans. Comput. Syst. (TOCS) 34, 2 (2016), 6.
-
(2016)
ACM Trans. Comput. Syst. (TOCS)
, vol.34
, Issue.2
, pp. 6
-
-
Lo, D.1
Cheng, L.2
Govindaraju, R.3
Ranganathan, P.4
Kozyrakis, C.5
-
43
-
-
0014701246
-
Evaluation techniques for storage hierarchies
-
1970
-
Richard L. Mattson, Jan Gecsei, Donald R. Slutz, and Irving L. Traiger. 1970. Evaluation techniques for storage hierarchies. IBM Systems Journal 9, 2 (1970), 78-117.
-
(1970)
IBM Systems Journal
, vol.9
, Issue.2
, pp. 78-117
-
-
Mattson, R.L.1
Gecsei, J.2
Slutz, D.R.3
Traiger, I.L.4
-
45
-
-
85019899962
-
-
OSU-CSE News
-
OSU-CSE News. 2010. Intel Puts OSU-CSE Inside. Retrieved from http://web.cse.ohio-state.edu/news/news118.shtml.
-
(2010)
Intel Puts OSU-CSE Inside
-
-
-
47
-
-
84958770551
-
A survey of architectural techniques for managing process variation
-
2016
-
Sparsh Mittal. 2016a. A survey of architectural techniques for managing process variation. Comput. Surveys 48, 4 (2016), 54:1-54:29.
-
(2016)
Comput. Surveys
, vol.48
, Issue.4
, pp. 541-5429
-
-
Mittal, S.1
-
48
-
-
84965128688
-
A survey of cache bypassing techniques
-
2016
-
Sparsh Mittal. 2016b. A survey of cache bypassing techniques. J. Low Power Elect. Appl. 6, 2 (2016), 5:1-5:30.
-
(2016)
J. Low Power Elect. Appl.
, vol.6
, Issue.2
, pp. 51-530
-
-
Mittal, S.1
-
49
-
-
84905112592
-
MASTER: A multicore cache energy saving technique using dynamic cache reconfiguration
-
2014
-
Sparsh Mittal, Yanan Cao, and Zhao Zhang. 2014a. MASTER: A multicore cache energy saving technique using dynamic cache reconfiguration. IEEE Trans. VLSI Syst. 22, 8 (2014), 1653-1665.
-
(2014)
IEEE Trans. VLSI Syst.
, vol.22
, Issue.8
, pp. 1653-1665
-
-
Mittal, S.1
Cao, Y.2
Zhang, Z.3
-
51
-
-
84939814753
-
A survey of CPU-GPU heterogeneous computing techniques
-
2015
-
Sparsh Mittal and Jeffrey Vetter. 2015. A survey of CPU-GPU heterogeneous computing techniques. Comput. Surveys 47, 4 (2015), 69:1-69:35.
-
(2015)
Comput. Surveys
, vol.47
, Issue.4
, pp. 691-6935
-
-
Mittal, S.1
Vetter, J.2
-
52
-
-
84969930755
-
A survey of techniques for architecting DRAM caches
-
2016
-
Sparsh Mittal and Jeffrey Vetter. 2016. A survey of techniques for architecting DRAM caches. IEEE Trans. Parallel. Distrib. Syst. (TPDS) 27, 6 (2016), 1852-1863.
-
(2016)
IEEE Trans. Parallel. Distrib. Syst. (TPDS)
, vol.27
, Issue.6
, pp. 1852-1863
-
-
Mittal, S.1
Vetter, J.2
-
53
-
-
84929352865
-
A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches
-
2015
-
Sparsh Mittal, Jeffrey S. Vetter, and Dong Li. 2015. A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches. IEEE Trans. Parallel Distrib. Syst. (TPDS) 26, 6 (2015), 1524-1537.
-
(2015)
IEEE Trans. Parallel Distrib. Syst. (TPDS)
, vol.26
, Issue.6
, pp. 1524-1537
-
-
Mittal, S.1
Vetter, J.S.2
Li, D.3
-
55
-
-
70449655189
-
FlexDCP: A QoS framework for CMP architectures
-
2009
-
Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Rizos Sakellariou, and Mateo Valero. 2009. FlexDCP: A QoS framework for CMP architectures. ACM SIGOPS Operat. Syst. Rev. 43, 2 (2009), 86- 96.
-
(2009)
ACM SIGOPS Operat. Syst. Rev.
, vol.43
, Issue.2
, pp. 86-96
-
-
Moreto, M.1
Cazorla, F.J.2
Ramirez, A.3
Sakellariou, R.4
Valero, M.5
-
58
-
-
58049192643
-
An adaptive Bloom filter cache partitioning scheme for multicore architectures
-
Konstantinos Nikas, Matthew Horsnell, and Jim Garside. 2008. An adaptive Bloom filter cache partitioning scheme for multicore architectures. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08). 25-32.
-
(2008)
Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08)
, pp. 25-32
-
-
Nikas, K.1
Horsnell, M.2
Garside, J.3
-
59
-
-
80053045712
-
An analytical performance model for co-management of last-level cache and bandwidth sharing
-
Taecheol Oh, Kiyeon Lee, and Sangyeun Cho. 2011. An analytical performance model for co-management of last-level cache and bandwidth sharing. In Proceedings of the 2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS' 11). 150-158.
-
(2011)
Proceedings of the 2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS' 11)
, pp. 150-158
-
-
Oh, T.1
Lee, K.2
Cho, S.3
-
61
-
-
34548027653
-
Stat- Share: A statistical model for managing cache sharing via decay
-
Pavlos Petoumenos, Georgios Keramidas, Hakan Zeffer, Stefanos Kaxiras, and Erik Hagersten. 2006. Stat- Share: A statistical model for managing cache sharing via decay. In Proceedings of the Workshop on Modeling, Benchmarking and Simulation (MoBS'06).
-
(2006)
Proceedings of the Workshop on Modeling, Benchmarking and Simulation (MoBS'06)
-
-
Petoumenos, P.1
Keramidas, G.2
Zeffer, H.3
Kaxiras, S.4
Hagersten, E.5
-
62
-
-
34547636819
-
Explaining dynamic cache partitioning speed ups
-
2007
-
Miquel Moreto Planas, Francisco Cazorla, Alex Ramirez, and Mateo Valero. 2007. Explaining dynamic cache partitioning speed ups. IEEE Comput. Arch. Lett. 6, 1 (2007), 1-4.
-
(2007)
IEEE Comput. Arch. Lett.
, vol.6
, Issue.1
, pp. 1-4
-
-
Moreto Planas, M.1
Cazorla, F.2
Ramirez, A.3
Valero, M.4
-
63
-
-
35348920021
-
Adaptive insertion policies for high performance caching
-
(2007)
-
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely, and Joel Emer. 2007. Adaptive insertion policies for high performance caching. In Proceedings of the International Symposium on Computer Architecture (2007), 381-391.
-
(2007)
Proceedings of the International Symposium on Computer Architecture
, pp. 381-391
-
-
Qureshi, M.K.1
Jaleel, A.2
Patt, Y.N.3
Steely, S.C.4
Emer, J.5
-
66
-
-
77949462086
-
Cache partitioning for energy-efficient and interference-free embedded multitasking
-
2010
-
R. Reddy and P. Petrov. 2010. Cache partitioning for energy-efficient and interference-free embedded multitasking. ACM Trans. Embed. Comput. Syst. (TECS) 9, 3 (2010), 16.
-
(2010)
ACM Trans. Embed. Comput. Syst. (TECS)
, vol.9
, Issue.3
, pp. 16
-
-
Reddy, R.1
Petrov, P.2
-
69
-
-
68949199685
-
A dynamically reconfigurable cache for multithreaded processors
-
2006
-
Alex Settle, Dan Connors, Enric Gibert, and Antonio González. 2006. A dynamically reconfigurable cache for multithreaded processors. J. Embed. Comput. 2, 2 (2006), 221-233.
-
(2006)
J. Embed. Comput.
, vol.2
, Issue.2
, pp. 221-233
-
-
Settle, A.1
Connors, D.2
Gibert, E.3
González, A.4
-
70
-
-
74049129459
-
A case for integrated processor-cache partitioning in chip multiprocessors
-
Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, and Mahmut Kandemir. 2009a. A case for integrated processor-cache partitioning in chip multiprocessors. In Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis (SC'09). 6.
-
(2009)
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis (SC'09)
, pp. 6
-
-
Srikantaiah, S.1
Das, R.2
Mishra, A.K.3
Das, C.R.4
Kandemir, M.5
-
72
-
-
0026925878
-
Optimal partitioning of cache memory
-
1992
-
H. S. Stone, J. Turek, and J. L. Wolf. 1992. Optimal partitioning of cache memory. IEEE Trans. Comput. 41, 9 (1992), 1054-1068.
-
(1992)
IEEE Trans. Comput.
, vol.41
, Issue.9
, pp. 1054-1068
-
-
Stone, H.S.1
Turek, J.2
Wolf, J.L.3
-
73
-
-
84959900441
-
The application slowdown model: Quantifying and controlling the impact of inter-application interference at shared caches and main memory
-
Lavanya Subramanian, Vivek Seshadri, Arnab Ghosh, Samira Khan, and Onur Mutlu. 2015. The application slowdown model: Quantifying and controlling the impact of inter-application interference at shared caches and main memory. In Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'15). 62-75.
-
(2015)
Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'15)
, pp. 62-75
-
-
Subramanian, L.1
Seshadri, V.2
Ghosh, A.3
Khan, S.4
Mutlu, O.5
-
75
-
-
1642371317
-
Dynamic partitioning of shared cache memory
-
2004
-
G. E. Suh, L. Rudolph, and S. Devadas. 2004. Dynamic partitioning of shared cache memory. J. Supercomput. 28, 1 (2004), 7-26.
-
(2004)
J. Supercomput.
, vol.28
, Issue.1
, pp. 7-26
-
-
Suh, G.E.1
Rudolph, L.2
Devadas, S.3
-
76
-
-
51549114926
-
Exploring locking & partitioning for predictable shared caches on multi-cores
-
Vivy Suhendra and Tulika Mitra. 2008. Exploring locking & partitioning for predictable shared caches on multi-cores. In Proceedings of the Design Automation Conference. 300-303.
-
(2008)
Proceedings of the Design Automation Conference
, pp. 300-303
-
-
Suhendra, V.1
Mitra, T.2
-
77
-
-
84860335317
-
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs
-
Karthik T. Sundararajan, Vasileios Porpodas, Timothy M. Jones, Nigel P. Topham, and Bjorn Franke. 2012. Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs. In Proceedings of the International Symposium on High-Performance Computer Architecture, (2012), 1-12.
-
(2012)
Proceedings of the International Symposium on High-Performance Computer Architecture, (2012)
, pp. 1-12
-
-
Sundararajan, K.T.1
Porpodas, V.2
Jones, T.M.3
Topham, N.P.4
Franke, B.5
-
79
-
-
40349093471
-
Molecular caches: A caching structure for dynamic creation of application-specific heterogeneous cache regions
-
Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Amrutur Bharadwaj, Ravi Iyer, Srihari Makineni, and Donald Newell. 2006. Molecular caches: A caching structure for dynamic creation of application-specific heterogeneous cache regions. In Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06). 433-442.
-
(2006)
Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)
, pp. 433-442
-
-
Varadarajan, K.1
Nandy, S.K.2
Sharda, V.3
Bharadwaj, A.4
Iyer, R.5
Makineni, S.6
Newell, D.7
-
81
-
-
84865689576
-
Cache latency control for application fairness or differentiation in power-constrained chip multiprocessors
-
2012
-
XiaoruiWang, KaiMa, and YefuWang. 2012. Cache latency control for application fairness or differentiation in power-constrained chip multiprocessors. IEEE Trans. Comput. 61, 10 (2012), 1371-1385.
-
(2012)
IEEE Trans. Comput.
, vol.61
, Issue.10
, pp. 1371-1385
-
-
Wang, X.1
Ma, K.2
Wang, Y.3
-
83
-
-
70450279102
-
PIPP: Promotion/insertion pseudo-partitioning of multi-core shared caches
-
ACM
-
Y. Xie and G. H. Loh. 2009. PIPP: Promotion/insertion pseudo-partitioning of multi-core shared caches. In ACM SIGARCH Computer Architecture News, Vol. 37. ACM, 174-183.
-
(2009)
ACM SIGARCH Computer Architecture News
, vol.37
, pp. 174-183
-
-
Xie, Y.1
Loh, G.H.2
-
87
-
-
77956204832
-
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
-
Chenjie Yu and Peter Petrov. 2010. Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms. In Proceedings of the Design Automation Conference. 132-137.
-
(2010)
Proceedings of the Design Automation Conference
, pp. 132-137
-
-
Yu, C.1
Petrov, P.2
-
89
-
-
84903639864
-
CLU: Co-optimizing locality and utility in threadaware capacity management for shared last level caches
-
2014
-
Dongyuan Zhan, Hong Jiang, and Sharad C. Seth. 2014. CLU: Co-optimizing locality and utility in threadaware capacity management for shared last level caches. IEEE Trans. Comput. 63, 7 (2014), 1656-1667.
-
(2014)
IEEE Trans. Comput.
, vol.63
, Issue.7
, pp. 1656-1667
-
-
Zhan, D.1
Jiang, H.2
Seth, S.C.3
-
91
-
-
84857877836
-
Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems
-
2012
-
Miao Zhou, Yu Du, Bruce Childers, Rami Melhem, and Daniel Mossé. 2012. Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems. ACM Trans. Arch. Code Optim. (TACO) 8, 4 (2012), 53.
-
(2012)
ACM Trans. Arch. Code Optim. (TACO)
, vol.8
, Issue.4
, pp. 53
-
-
Zhou, M.1
Du, Y.2
Childers, B.3
Melhem, R.4
Mossé, D.5
-
92
-
-
84954324136
-
Symmetry-agnostic coordinated management of the memory hierarchy in multicore systems
-
2016
-
Miao Zhou, Yu Du, Bruce Childers, Daniel Mosse, and Rami Melhem. 2016. Symmetry-agnostic coordinated management of the memory hierarchy in multicore systems. ACM Trans. Arch. Code Optim. (TACO) 12, 4 (2016), 61.
-
(2016)
ACM Trans. Arch. Code Optim. (TACO)
, vol.12
, Issue.4
, pp. 61
-
-
Zhou, M.1
Du, Y.2
Childers, B.3
Mosse, D.4
Melhem, R.5
|