Latency-aware utility-based NUCA cache partitioning in 3D-stacked multi-processor systems

Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010

Volumn , Issue , 2010, Pages 125-130

  Jung, Jongpil ^a   Kim, Seonpil ^a   Kyung, Chong Min ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PROGRAMS; CACHE ACCESS; CACHE PARTITIONING; CONVENTIONAL METHODS; DRIVING FORCES; LATENCY VARIATIONS; LATENCY-AWARE; MEMORY ACCESS TIME; MULTIPROCESSOR-SYSTEM; NON-UNIFORM CACHE ARCHITECTURES; PROCESSOR CORES; THREE DIMENSIONAL INTEGRATION; UTILITY-BASED;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; MULTIPROCESSING SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; THREE DIMENSIONAL;

CACHE MEMORY;

EID: 78650939759     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2010.5642608     Document Type: Conference Paper

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