A Survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches

IEEE Transactions on Parallel and Distributed Systems

Volumn 26, Issue 6, 2015, Pages 1524-1537

  Mittal, Sparsh ^a   Vetter, Jeffrey S ^a   Li, Dong ^a  

^a OAK RIDGE NATIONAL LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; INTEGRATED CIRCUIT DESIGN; PHASE CHANGE MEMORY; RANDOM ACCESS STORAGE; STATIC RANDOM ACCESS STORAGE; SURVEYS;

ARCHITECTURAL APPROACH; COMPUTING SYSTEM; DEVICE TECHNOLOGIES; EMERGING MEMORY; EMERGING MEMORY TECHNOLOGIES; KEY CHARACTERISTICS; PHASE CHANGE RAMS; SPIN TRANSFER TORQUE;

CACHE MEMORY;

EID: 84929352865     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2014.2324563     Document Type: Review

References (113)

1. P. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, Al Scarpelli, S. Scott, A. Snavely, T. Sterling, R. S. Williams, and K. Yelick, Exascale computing study: Technology challenges in achieving exascale systems, DARPA Inf. Process. Techn. Office, Arlington, VA, USA, Tech. Rep. TR-2008-13, 2008.
2. J. Dongarra, P. Beckman, T. Moore, P. Aerts, G. Aloisio, J.-C. Andre, D. Barkai, J.-Y. Berthou, T. Boku, B. Braunschweig, F. Cappello, B. Chapman, X. Chi, A. Choudhary, S. Dosanjh, T. Dunning, S. Fiore, A. Geist, B. Gropp, R. Harrison, M. Hereld, M. Heroux, A. Hoisie, K. Hotta, Z. Jin, Y. Ishikawa, F. Johnson, S. Kale, R. Kenway, D. Keyes, B. Kramer, J. Labarta, A. Lichnewsky, T. Lippert, B. Lucas, B. Maccabe, S. Matsuoka, P. Messina, P. Michielse, B. Mohr, M. S. Mueller, W. E. Nagel, H. Nakashima, M. E. Papka, D. Reed, M. Sato, E. Seidel, J. Shalf, D. Skinner, M. Snir, T. Sterling, R. Stevens, F. Streitz, B. Sugar, S. Sumimoto, W. Tang, J. Taylor, R. Thakur, A. Trefethen, M. Valero, A. van der Steen, J. Vetter, P. Williams, R. Wisniewski, and K. Yelick, The international exascale software project roadmap, Int. J. High Perform. Comput. Appl., vol. 25, no. 1, pp. 3-60, 2011.
3. Intel. (2014). [Online]. Available: http://ark.intel.com/products/53580.
4. S. Mittal, A survey of architectural techniques for improving cache power efficiency, Sustainable Comput.: Inf. Syst., vol. 4, no. 1, pp. 33-43, 2014.
5. B. M. Rogers, A. Krishna, G. B. Bell, K. Vu, X. Jiang, and Y. Solihin, Scaling the bandwidth wall: Challenges in and avenues for CMP scaling, in Proc. 36th Annu. Int. Symp. Comput. Archit., 2009, pp. 371-382.
6. M. K. Qureshi, S. Gurumurthi, and B. Rajendran, Phase change memory: From devices to systems, Synthesis Lect. Comput. Archit., vol. 6, no. 4, pp. 1-134, 2011.
7. Y. Li, Y. Chen, and A. K. Jones, A software approach for combating asymmetries of non-volatile memories, in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des., 2012, pp. 191-196.
8. S.-M. Syu, Y.-H. Shao, and I.-C. Lin, High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy, in Proc. 23rd ACM Int. Conf. Great Lakes Symp. VLSI, 2013, pp.19-24.
9. S. Mittal, Energy saving techniques for phase change memory (PCM), Iowa State Univ., Ames, IA, USA, Tech. Rep., 2013.
10. X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony, and Y. Xie, Hybrid cache architecture with disparate memory technologies, in Proc. 36th Annu. Int. Symp. Comput, Archit., 2009, pp. 34-45.
11. M.-T. Chang, P. Rosenfeld, S.-L. Lu, and B. Jacob, Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM, in Proc. IEEE 19th Int. Symp. High Perform. Comput. Archit., 2013, pp.143-154.
12. Y.-T. Chen, J. Cong, H. Huang, B. Liu, C. Liu, M. Potkonjak, and G. Reinman, Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design, in Proc. Des., Autom. Test Eur. Conf. Exhib., 2012, pp. 45-50.
13. C. W. Smullen, V. Mohan, A. Nigam, S. Gurumurthi, and M. R. Stan, Relaxing non-volatility for fast and energy-efficient STTRAM caches, in Proc. IEEE 17th Int. Symp. High Perform. Comput. Archit., 2011, pp. 50-61.
14. J. Zhao, C. Xu, and Y. Xie, Bandwidth-aware reconfigurable cache design with hybrid memory technologies, in Proc. IEEE Int. Conf. Comput.-Aided Des., 2010, pp. 48-55.
15. X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen, Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement, in Proc. IEEE 45th Des. Autom. Conf., 2008, pp. 554-559.
16. S. Mittal, Z. Zhang, and Y. Cao, CASHIER: A cache energy saving technique for QoS systems, in Proc. 26th Int. Conf. VLSI Des. 12th Int. Conf. Embedded Syst., 2013, pp. 43-48.
17. M. H. Kryder and C. S. Kim, After hard drives-what comes next? IEEE Trans. Magn., vol. 45, no. 10, pp. 3406-3413, Oct. 2009.
18. R. Venkatesan, V. Kozhikkottu, C. Augustine, A. Raychowdhury, K. Roy, and A. Raghunathan, TapeCache: A high density, energy efficient cache based on domain wall memory, in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des., 2012, pp.185-190.
19. M. Rasquinha, D. Choudhary, S. Chatterjee, S. Mukhopadhyay, and S. Yalamanchili, An energy efficient cache design using spin torque transfer (STT) RAM, in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des., 2010, pp. 389-394.
20. (2014). [Online]. Available: http://www.mram-info.com/companies
21. (2014). [Online]. Available: http://www.memorystrategies. com/report/embeddeddram.html
22. (2014). [Online]. Available: http://www.economist.com/node/21560981
23. R. Kalla, B. Sinharoy, W. J. Starke, and M. Floyd, Power7: IBMs next-generation server processor, IEEE Micro, vol. 30, no. 2, pp. 7-15, Mar./Apr. 2010.
24. S. S. Iyer, J. E. Barth Jr., P. C. Parries, J. P. Norum, J. P. Rice, L. R. Logan, and D. Hoyniak, Embedded DRAM: Technology platform for the Blue Gene/L chip, IBM J. Res. Develop., vol. 49, pp. 333-350, 2005.
25. N. Kurd, M. Chowdhury, E. Burton, T. P. Thomas, C. Mozak, B. Boswell, M. Lal, A. Deval, J. Douglas, M. Elassal, A. Nalamalpu, T. M. Wilson, M. Merten, S. Chennupaty, W. Gomes, and R. Kumar, Haswell: A family of IA 22nm processors, in Proc. IEEE Int. Solid-State Circuits Conf. Digest Tech. Papers, 2014, pp.112-113.
26. A. Agrawal, P. Jain, A. Ansari, and J. Torrellas, Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies, in Proc. Conf. High Perform. Comput. Archit., 2013, pp. 400-411.
27. CACTI 5.3. (2014). [Online]. Available: http://quid.hpl.hp. com:9081/cacti/
28. J. Barth,W.R. Reohr, P. Parries, G.Fredeman, J. Golz, S. E. Schuster, R. E. Matick, H. Hunter, C. C. Tanner, J. Harig, H. Kim, B. A. Khan, J. Griesemer, R. P. Havreluk, K. Yanagisawa, T. Kirihata, and S. S. Iyer, A 500 MHz random cycle, 1.5 ns latency, SOI embedded DRAM macro featuring a three-transistor micro sense amplifier, IEEE J. Solid-State Circuit, vol. 43, no. 1, pp. 86-95, 2008.
29. C. Wilkerson, A. R. Alameldeen, Z. Chishti, W. Wu, D. Somasekhar, and S.-L. Lu, Reducing cache power with low-cost, multi-bit error-correcting codes, in Proc. 37th Annu. Int. Symp. Comput. Archit., 2010, pp. 83-93.
30. M. Alizadeh, A. Javanmard, S.-T. Chuang, S. Iyer, and Y. Lu, Versatile refresh: Low complexity refresh scheduling for highthroughput multi-banked eDRAM, ACM SIGMETRICS Perform. Eval. Rev., vol. 40, no. 1, pp. 247-258, 2012.
31. Y. Huai, Spin-transfer torque MRAM (STT-MRAM): Challenges and prospects, AAPPS Bull., vol. 18, no. 6, pp. 33-40, 2008.
32. A. Jog, A. K. Mishra, C. Xu, Y. Xie, V. Narayanan, R. Iyer, and C. R. Das, Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs, in Proc. IEEE/ACM Des. Autom. Conf., 2012, pp.243-252.
33. H. Li and Y. Chen, An overview of non-volatile memory technology and the implication for tools and architectures, in Proc. Des., Autom. Test Eur. Conf. Exhib., 2009, pp. 731-736.
34. Y.-B. Kim, S. R. Lee, D. Lee, C. B. Lee, M. Chang, J. H. Hur, M.-J. Lee, G.-S. Park, C. J. Kim, U.Chung, I.-K. Yoo, and K. Kim, Bi-layered RRAM with unlimited endurance and extremely uniform switching, in Proc. Symp. VLSI Technol., 2011, pp. 52-53.
35. X. Dong, C. Xu, Y. Xie, and N. P. Jouppi, NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 31, no. 7, pp. 994-1007, Jul. 2012.
36. J. Wang, X. Dong, Y. Xie, and N. P. Jouppi, i2WAP: Improving non-volatile cache lifetime by reducing inter-and intra-set write variations, in Proc. IEEE 19th Int. Symp. High Perform. Comput. Archit., 2013, pp. 234-245.
37. Y. Joo, D. Niu, X. Dong, G. Sun, N. Chang, and Y. Xie, Energyand endurance-aware design of phase change memory caches, in Proc. Design, Autom. Test Eur. Conf. Exhib., 2010, pp. 136-141.
38. R. Bishnoi, M. Ebrahimi, F. Oboril, and M. B. Tahoori, Avoiding unnecessary write operations in STT-MRAM for low power implementation, in Proc. 15th Int. Symp. Quality Electron. Des., 2014, pp. 548-553.
39. R. Bishnoi, M. Ebrahimi, F. Oboril, and M. Tahoori, Asynchronous asymmetrical write termination (AAWT) for a low power STT-MRAM, in Proc. Design, Autom. Test Eur. Conf. Exhib., 2014, pp. 1-6.
40. J. Lira, C. Molina, D. Brooks, and A. Gonzalez, Implementing a hybrid SRAM/eDRAM NUCA architecture, in Proc. IEEE 18th Int. Conf. High Perform. Comput., 2011, pp. 1-10.
41. A. Valero, J. Sahuquillo, S. Petit, V. Lorente, R. Canal, P. Lopez, and J. Duato, An hybrid eDRAM/SRAM macrocell to implement first-level data caches, in Proc. 42nd Annu. IEEE/ACM Int. Symp. Microarchit., 2009, pp. 213-221.
42. A. Valero, J. Sahuquillo, S. Petit, and J. Duato, Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches, in Proc. 27th Int. ACM Conf. Supercomput., 2013, pp. 491-492.
43. A. Valero, J. Sahuquillo, S. Petit, P. Lopez, and J. Duato, Analyzing the optimal ratio of SRAM banks in hybrid caches, in Proc. IEEE 30th Int. Conf. Comput. Des., 2012, pp. 297-302.
44. W. R. Reohr, Memories: Exploiting them and developing them, in Proc. IEEE Int. SOC Conf., 2006, pp. 303-310.
45. S. Mittal, A Cache reconfiguration approach for saving leakage and refresh energy in embedded DRAM caches, Iowa State Univ., Ames, IA, USA, Tech. Rep., 2013.
46. V. Lorente, A. Valero, J. Sahuquillo, S. Petit, R. Canal, P. Lopez, and J. Duato, Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes, in Proc. Design, Autom. Test Eur. Conf. Exhib., 2013, pp. 83-88.
47. S. Mittal, J. S. Vetter, and D. Li, Improving energy efficiency of embedded DRAM caches for high-end computing systems, in Proc. ACM 23rd Int. Symp. High Perform. Parallel Distrib. Comput., 2014.
48. A. Agrawal, A. Ansari, and J. Torrellas, Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules, in Proc. IEEE 19th Int. Symp. High Perform. Comput. Archit., 2014.
49. L. Jiang, B. Zhao, Y. Zhang, and J. Yang, Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors, in Proc. 49th ACM/EDAC/IEEE Des. Autom. Conf., 2012, pp. 907-912.
50. J. Ahn and K. Choi, Lower-bits cache for low power STT-RAM caches, in Proc. IEEE Int. Symp. Circuits Syst., 2012, pp. 480-483.
51. J. Wang, X. Dong, and Y. Xie, OAP: An obstruction-aware cache management policy for STT-RAM last-level caches, in Proc. Design, Autom. Test Eur. Conf. Exhib., 2013, pp. 847-852.
52. X. Bi, Z. Sun, H. Li, and W. Wu, Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches, in Proc. IEEE Int. Conf. Comput.-Aided Des., 2012, pp. 88-94.
53. J. Jung, Y. Nakata, M. Yoshimoto, and H. Kawaguchi, Energyefficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags, in Proc. Int. Symp. Quality Electron. Des., 2013, pp. 216-222.
54. Q. Li, J. Li, L. Shi, C. J. Xue, Y. Chen, and Y. He, Compilerassisted refresh minimization for volatile STT-RAM cache, in Proc. 18th Asia South Pacific Des. Autom. Conf., 2013, pp. 273-278.
55. B. Quan, T. Zhang, T. Chen, and J. Wu, Prediction table based management policy for STT-RAM and SRAM hybrid cache, in Proc. 7th Int. Conf. Comput. Convergence Technol., 2012, pp. 1092-1097.
56. S. Yazdanshenas, M. Ranjbar, M. Fazeli, and A. Patooghy, Coding last level STT-RAM cache for high endurance and low power, IEEE Comput. Archit. Lett., 2013, http://ieeexplore.ieee. org/xpl/login.jsp?tp=&arnumber=6514022&url=http%3A%2F% 2Fieeexplore.ieee.org%2Fxpls%2Fabs-all.jsp%3Farnumber% 3D6514022
57. J. Li, C. J. Xue, and Y. Xu, STT-RAM based energy-efficiency hybrid cache for CMPs, in Proc. IEEE/IFIP 19th Int. Conf. VLSI Syst.-on-Chip, 2011, pp. 31-36.
58. Q. Li, J. Li, L. Shi, C. J. Xue, and Y. He, Mac: Migration-aware compilation for STT-RAM based hybrid cache in embedded systems, in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des., 2012, pp. 351-356.
59. Q. Li, M. Zhao, C. J. Xue, and Y. He, Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache, ACM SIGPLAN Notices, vol. 47, no. 5, pp. 109-118, 2012.
60. Z. Sun, X. Bi, H. H. Li, W.-F. Wong, Z.-L. Ong, X. Zhu, and W. Wu, Multi retention level STT-RAM cache designs with a dynamic refresh scheme, in Proc. 44th Annu. IEEE/ACM Int. Symp. Microarchit., 2011, pp. 329-338.
61. G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen, A novel architecture of the 3D stacked MRAM L2 cache for CMPs, in Proc. IEEE Int. Symp. High Perform. Comput. Archit., 2009, pp.239-249.
62. H. Sun, C. Liu, N. Zheng, T. Min, and T. Zhang, Design techniques to improve the device write margin for MRAM-based cache memory, in Proc. ACM Int. Conf. Great Lakes Symp. VLSI, 2011, pp. 97-102.
63. X. Bi, H. Li, and J.-J. Kim, Analysis and optimization of thermal effect on STT-RAM Based 3-D stacked cache design, in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, 2012, pp. 374-379.
64. Y. Joo and S. Park, A hybrid PRAM and STT-RAM cache architecture for extending the lifetime of PRAM caches, Comput. Archit. Lett., vol. 12, no. 2, pp. 55-58, Jul./Dec. 2013.
65. B.-M. Lee and G.-H. Park, Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM, in Proc. Int. SoC Des. Conf., 2012, pp. 247-250.
66. M. Mao, H. L. Li, A. K. Jones, and Y. Chen, Coordinating prefetching and STT-RAM based last-level cache management for multicore systems, in Proc. ACM Int. Conf. Great Lakes Symp. VLSI, 2013, pp. 55-60.
67. Y. Li and A. K. Jones, Cross-layer techniques for optimizing systems utilizing memories with asymmetric access characteristics, in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, 2012, pp. 404-409.
68. H. Sun, C. Liu, W. Xu, J. Zhao, N. Zheng, and T. Zhang, Using magnetic RAM to build low-power and soft error-resilient L1 cache, IEEE Trans. Very Large Scale Integr. Syst., vol. 20, no. 1, pp. 19-28, Jan. 2012.
69. Y.-T. Chen, J. Cong, H. Huang, C. Liu, R. Prabhakar, and G. Reinman, Static and dynamic co-optimizations for blocks mapping in hybrid caches, in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des., 2012.
70. G. Sun, E. Kursun, J. A. Rivers, and Y. Xie, Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory, in Proc. IEEE 29th Int. Conf. Comput. Des., 2011, pp. 366-372.
71. H. Naeimi, C. Augustine, A. Raychowdhury, S.-L. Lu, and J. Tschanz, STTRAM scaling and retention failure, Intel Technol. J., vol. 17, no. 1, p. 54, 2013.
72. J. Li, L. Shi, Q. Li, C. J. Xue, Y. Chen, and Y. Xu, Cache coherence enabled adaptive refresh for volatile STT-RAM, in Proc. Des., Autom. Test Eur. Conf. Exhib., 2013, pp. 1247-1250.
73. J. Ahn, S. Yoo, and K. Choi, Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches, in Proc. Asia South Pacific Des. Autom. Conf., 2013, pp. 285-290.
74. Z. Sun, X. Bi, and H. Li, Process variation aware data management for STT-RAM cache design, in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des., 2012, pp. 179-184.
75. Y. Zhou, C. Zhang, G. Sun, K. Wang, and Y. Zhang, Asymmetric-access aware optimization for STT-RAM caches with process variations, in Proc. ACM Int. Conf. Great Lakes Symp. VLSI, 2013, pp. 143-148.
76. S. Lee, J. Jung, and C.-M. Kyung, Hybrid cache architecture replacing SRAM cache with future memory technology, in Proc. IEEE Int. Symp. Circuits Syst., 2012, pp. 2481-2484.
77. V. Saripalli, G. Sun, A. Mishra, Y. Xie, S. Datta, and V. Narayanan, Exploiting heterogeneity for energy efficiency in chip multiprocessors, IEEE J. Emerging Select. Topics Circuits Syst., vol. 1, no. 2, pp. 109-119, Jun. 2011.
78. H. Li, X. Wang, Z.-L. Ong, W.-F. Wong, Y. Zhang, P. Wang, and Y. Chen, Performance, power, and reliability tradeoffs of STTRAM cell subject to architecture-level requirement, IEEE Trans. Magn., vol. 47, no. 10, pp. 2356-2359, Oct. 2011.
79. Y. Chen, W.-F. Wong, H. Li, C.-K. Koh, Y. Zhang, and W. Wen, On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations, J. Emerg. Technol. Comput. Syst., vol. 9, no. 2, pp. 16:1-16:22, 2013.
80. P. Zhou, B. Zhao, J. Yang, and Y. Zhang, Energy reduction for STT-RAM using early write termination, in Proc. IEEE Int. Conf. Comput.-Aided Des., 2009, pp. 264-268.
81. S. P. Park, S. Gupta, N. Mojumder, A. Raghunathan, and K. Roy, Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture, in Proc. 49th Des. Autom. Conf., 2012, pp. 492-497.
82. A. Jadidi, M. Arjomand, and H. Sarbazi-Azad, High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement, in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des., 2011, pp. 79-84.
83. L. V. Cargnini, L. Torres, R. M. Brum, S. Senni, and G. Sassatelli, Embedded memory hierarchy exploration based on magnetic RAM, in Proc. IEEE Faible Tension Faible Consommation, 2013, pp. 1-4.
84. A. Sharifi and M. Kandemir, Automatic feedback control of shared hybrid caches in 3D chip multiprocessors, in Proc. Euromicro Int. Conf. Parallel, Distrib. Netw.-Based Process., 2011, pp. 393-400.
85. K. Swaminathan, E. Kultursay, V. Saripalli, V. Narayanan, and M. Kandemir, Design space exploration of workload-specific last-level caches, in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des., 2012, pp. 243-248.
86. S. Mittal, Using cache-coloring to mitigate inter-set write variation in non-volatile caches, Iowa State Univ., Ames, IA, USA, Tech. Rep., 2013.
87. J. Ahn and K. Choi, LASIC: Loop-aware sleepy instruction caches based on STT-RAM technology, IEEE Trans. Very Large Scale Integr. Syst., vol. 22, no. 5, pp. 1197-1201, May 2014.
88. K.-W. Kwon, S. H. Choday, Y. Kim, and K. Roy, AWARE (Asymmetric Write Architecture with REdundant blocks): A High Write Speed STT-MRAM Cache Architecture, IEEE Trans. Very Large Scale Integr. Syst., vol. 22, no. 4, pp. 712-720, Apr. 2014.
89. J. Ahn, S. Yoo, and K. Choi, Write intensity prediction for energy-efficient non-volatile caches, in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des., 2013, pp. 223-228.
90. Z. Sun, H. Li, and W. Wu, A dual-mode architecture for fastswitching STT-RAM, in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des., 2012, pp. 45-50.
91. R. Venkatesan, M. Sharad, K. Roy, and A. Raghunathan, DWMTAPESTRI-an energy efficient all-spin cache using domain wall shift based writes, in Proc. Des., Autom. Test Eur. Conf. Exhib., 2013, pp. 1825-1830.
92. N. Goswami, B. Cao, and T. Li, Power-performance co-optimization of throughput core architecture using resistive memory, in Proc. IEEE Int. Symp. High Perform. Comput. Archit., 2013, pp. 342-353.
93. Y. Li, Y. Zhang, H. Li, Y. Chen, and A. K. Jones, C1C: A configurable, compiler-guided STT-RAM L1 cache, ACM Trans. Archit. Code Optimization, vol. 10, no. 4, pp. 52:1-52:22, 2013.
94. J. Zhao and Y. Xie, Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration, in Proc. IEEE Int. Conf. Comput.-Aided Des., 2012, pp. 81-87.
95. N. Strikos, V. Kontorinis, X. Dong, H. Homayoun, and D. Tullsen, Low-current probabilistic writes for power-efficient STT-RAM caches, in Proc. IEEE 31st Int. Conf. Comput. Des., 2013, pp. 511-514.
96. S. Mittal, J. S. Vetter, and D. Li, LastingNVCache: A technique for improving the lifetime of non-volatile caches, in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, 2014.
97. X. Dong, N. P. Jouppi, and Y. Xie, A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies, in Proc. IEEE Int. Symp. Perform. Anal. Syst. Softw., 2013, pp. 140-141.
98. S. Mittal J. S. Vetter, and D. Li, WriteSmoothing: Improving Lifetime of Non-volatile Caches Using Intra-set Wear-leveling, in Proc. ACM Int. Conf. Great Lakes Symp. VLSI, 2014.
99. P. Mangalagiri, K. Sarpatwari, A. Yanamandra, V. Narayanan, Y. Xie, M. J. Irwin, and O. A. Karim, A low-power phase change memory based hybrid cache architecture, in Proc. ACM Int. Conf. Great Lakes Symp. VLSI, 2008, pp. 395-398.
100. S. Guo, Z. Liu, D. Wang, H. Wang, and G. Li, Wear-resistant hybrid cache architecture with phase change memory, in Proc. IEEE 7th Int. Conf. Netw., Archit. Storage, 2012, pp. 268-272.
101. M. Sharad, R. Venkatesan, A. Raghunathan, and K. Roy, Multilevel magnetic RAM using domain wall shift for energy-efficient, high-density caches, in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des., 2013, pp. 64-69.
102. Z. Sun, W. Wu, and H. Li, Cross-layer racetrack memory design for ultra high density and low power consumption, in Proc. 45th Des. Autom. Conf., 2013, pp. 1-6.
103. J. Li, L. Shi, C. J. Xue, C. Yang, and Y. Xu, Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache, in Proc. IEEE 9th Symp. Embedded Syst. Real-Time Multimedia, 2011, pp. 19-28.
104. H. Noguchi, K. Nomura, K. Abe, S. Fujita, E. Arima, K. Kim, T. Nakada, S. Miwa, and H. Nakamura, D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory, in Proc. Des., Autom. Test Eur. Conf. Exhib., 2013, pp. 1813-1818.
105. A. Al Maashri, G. Sun, X. Dong, V. Narayanan, and Y. Xie, 3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis, in Proc. IEEE Int. Conf. Comput. Des., 2009, pp. 254-259.
106. P. Satyamoorthy, STT-RAM for shared memory in GPUs, Ph.D. dissertation, Faculty School Eng. Appl. Sci., Univ. Virginia, Charlottesville, VA, USA, 2011.
107. X. Guo, E. Ipek, and T. Soyata, Resistive computation: Avoiding the power wall with low-leakage, STT-MRAM based computing, in Proc. 37th Annu. Int. Symp. Comput. Archit., 2010, pp. 371-382.
108. X. Bi, M. Mao, D. Wang, and H. Li, Unleashing the potential of MLC STT-RAM caches, in Proc. IEEE Int. Conf. Comput.-Aided Des., 2013, pp. 429-436.
109. Y. Xie, Future memory and interconnect technologies, in Proc. Des., Autom. Test Eur. Conf. Exhib., 2013, pp. 964-969.
110. S. Kaxiras, Z. Hu, and M. Martonosi, Cache decay: Exploiting generational behavior to reduce cache leakage power, in Proc. 28th Annu. Int. Symp. Comput. Archit., 2001, pp. 240-251.
111. S. Mittal, Z. Zhang, and J. S. Vetter, FlexiWay: A cache energy saving technique using fine-grained cache reconfiguration, in Proc. 31st Int. Conf. Comput. Des., 2013, pp. 100-107.
112. S. Mittal, Y. Cao, and Z. Zhang, MASTER: A multicore cache energy saving technique using dynamic cache reconfiguration, IEEE Trans. Very Large Scale Integr. Syst., 2013.
113. G. Sun, C. Hughes, C. Kim, J. Zhao, C. Xu, Y. Xie, and Y.-K. Chen, Moguls: A model to explore the memory hierarchy for bandwidth improvements, in Proc. 38th Annu. Int. Symp. Comput. Archit., 2011, pp. 377-388.