CloudCache: Expanding and shrinking private caches

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2011, Pages 219-230

  Lee, Hyunjin ^a   Cho, Sangyeun ^a   Childers, Bruce R ^a  

^a UNIVERSITY OF PITTSBURGH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS LATENCY; ARCHITECTURAL COMPONENTS; CACHE MANAGEMENT; CACHE PARTITIONING; COHERENCE PROTOCOL; EXPERIMENTAL EVALUATION; L2 CACHE; MONITORING AND CONTROL; ON-CHIP CACHE; POWER WALLS; SINGLE-CHIP MULTIPROCESSORS;

CACHE MEMORY; MICROPROCESSOR CHIPS; SHRINKAGE;

COMPUTER ARCHITECTURE;

EID: 79955893556     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2011.5749731     Document Type: Conference Paper

References (27)

1. M. Azimi et al. Integration challenges and trade-offs for terascale architectures. Intel Tech. J., 11(3):173-184, August 2007.
2. L. Seiler et al. Larrabee: a many-core x86 architecture for visual computing. Intel Tech. J., 27(3):1-15, August 2008.
3. Tilera. Tilera announces the world's first 100-core processor with the new tile-gx family. http://www.tilera.com/news-&-events/press-release- 091026.php.
4. Tensilica. Tensilica - servers, storage, and communications infrastructure. http://www.tensilica.com/markets/networking-storage.htm.
5. M. Zhang et al. Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors. ISCA, 2005.
6. Z. Chishti et al. Optimizing replication, communication, and capacity allocation in cmps. ISCA, 2005.
7. J. Chang and G. S. Sohi. Cooperative caching for chip multiprocessors. ISCA, 2006.
8. B Beckmann et al. Asr: Adaptive selective replication for cmp caches. MICRO, 2006.
9. M. K. Qureshi. Adaptive spill-receive for robust high-performance caching in cmps. HPCA, 2009.
10. H. Hardavellas et al. Reactive nuca: near-optimal block placement and replication in distributed caches. ISCA, 2009.
11. D. Kaseridis et al. Bank-aware dynamic cache partitioning for multicore architectures. ICPP, 2009.
12. A. Esser. Best practices for unlocking your hidden data center. http://www.dell.com/downloads/global/power/ps1q08-20080198-Esse.pdf.
13. J. M. Kaplan et al. Revolutionizing data center energy efficiency. http://www.mckinsey.com/clientservice/btopointofview/pdf/Revolutionizing-Data- Center-Efficiency.pdf.
14. B. Beckmann and D. Wood. Managing wire delay in large chip-multiprocessor caches,. MICRO, 2004.
15. J. Huh et al. A nuca substrate for flexible cmp cache sharing. ICS, 2005.
16. M. K. Qureshi et al. Utility-based partitioning of shared caches. MICRO, 2006.
17. M. R. Marty et al. Virtual hierarchies to support server consolidation. ISCA, 2007.
18. K. J. Nesbit et al. Virtual private caches. ISCA, 2007.
19. H. Lee et al. Stimuluscache: Boosting performance of chip multiprocessors with excess cache. HPCA, 2010.
20. E. Herrero et al. Elastic cooperative caching: An autonomous dynamically adaptive memory hierarchy for chip multiprocessors. ISCA, 2010.
21. J. Tendler et al. Power4 system microarchitecture. IBM Technical White Paper, October 2001.
22. D. Seo et al. Near-optimal worst-case throughput routing for two-dimensional mesh networks. ISCA, 2005.
23. M. Plakal et al. Lamport clocks: Verifying a directory cachecoherence protocol. SPAA, 1998.
24. A. Gupta et al. Reducing memory and traffic requirements for scalable directory-based cache coherence schemes. ICPP, 1990.
25. H. Lee et al. Two-phase trace-driven simulation (tpts): A fast multicore processor architecture simulation approach. Software: Practice and Experience (SPE), March 2010.
26. C. Bienia et al. The parsec benchmark suite: Characterization and arch. implications. PACT, 2008.
27. A. Snavely et al. Symbiotic job scheduling for a simultaneous multithreading processor. ASPLOS, 2005.