-
1
-
-
40549144540
-
-
ARM920T. Technical Reference Manual. http://infocenter.arm.com/help/ topic/com.arm.doc.ddi0151c/ARM920T-TRM1-S.pdf.
-
Technical Reference Manual
-
-
-
4
-
-
33744824945
-
Predictable performance in SMT processors: Synergy between the OS and SMTs
-
DOI 10.1109/TC.2006.108
-
F. J. Cazorla, P. M. W. Knijnenburg, R. Sakellariou, E. Fernandez, A. Ramirez, and M. Valero. Predictable performance in SMT processors: Synergy between the OS and SMTs. IEEE ToC, 55(7):785-799, 2006. (Pubitemid 43834513)
-
(2006)
IEEE Transactions on Computers
, vol.55
, Issue.7
, pp. 785-799
-
-
Cazorla, F.J.1
Knijnenburg, P.M.W.2
Sakellariou, R.3
Fernandez, E.4
Ramirez, A.5
Valero, M.6
-
6
-
-
47349085427
-
A framework for providing quality of service in chip multi-processors
-
F. Guo, Y. Solihin, L. Zhao, and R. Iyer. A framework for providing quality of service in chip multi-processors. In MICRO, 2007.
-
(2007)
MICRO
-
-
Guo, F.1
Solihin, Y.2
Zhao, L.3
Iyer, R.4
-
7
-
-
0031235242
-
A single-chip multiprocessor
-
L. Hammond, B. A. Nayfeh, and K. Olukotun. A single-chip multiprocessor. Computer, 30(9):79-85, 1997.
-
(1997)
Computer
, vol.30
, Issue.9
, pp. 79-85
-
-
Hammond, L.1
Nayfeh, B.A.2
Olukotun, K.3
-
8
-
-
4043131877
-
Millicode in an IBM zSeries processor
-
L. C. Heller and M. S. Farrell. Millicode in an IBM zSeries processor. IBM J. Res. Dev., 48(3-4):425-434, 2004.
-
(2004)
IBM J. Res. Dev.
, vol.48
, Issue.3-4
, pp. 425-434
-
-
Heller, L.C.1
Farrell, M.S.2
-
10
-
-
34247143442
-
Communist, utilitarian, and capitalist cache policies on CMPs: Caches as a shared resource
-
L. R. Hsu, S. K. Reinhardt, R. Iyer, and S. Makineni. Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource. In PACT, 2006.
-
(2006)
PACT
-
-
Hsu, L.R.1
Reinhardt, S.K.2
Iyer, R.3
Makineni, S.4
-
11
-
-
0034845925
-
Variability in the execution of multimedia applications and implications for architecture
-
C. J. Hughes, P. Kaul, S. V. Adve, R. Jain, C. Park, and J. Srinivasan. Variability in the execution of multimedia applications and implications for architecture. In ISCA, 2001.
-
(2001)
ISCA
-
-
Hughes, C.J.1
Kaul, P.2
Adve, S.V.3
Jain, R.4
Park, C.5
Srinivasan, J.6
-
12
-
-
67650595791
-
QoS policies and architecture for cache/memory in CMP platforms
-
R. R. Iyer, L. Zhao, F. Guo, R. Illikkal, S. Makineni, D. Newell, Y. Solihin, L. R. Hsu, and S. K. Reinhardt. QoS policies and architecture for cache/memory in CMP platforms. In SIGMETRICS, 2007.
-
(2007)
SIGMETRICS
-
-
Iyer, R.R.1
Zhao, L.2
Guo, F.3
Illikkal, R.4
Makineni, S.5
Newell, D.6
Solihin, Y.7
Hsu, L.R.8
Reinhardt, S.K.9
-
13
-
-
63549149925
-
Adaptive insertion policies for managing shared caches on cmps
-
A. Jaleel, W. Hasenplaugh, M. K. Qureshi, J. Sebot, S. C. S. Jr, and J. Emer. Adaptive insertion policies for managing shared caches on cmps. In PACT, 2008.
-
(2008)
PACT
-
-
Jaleel, A.1
Hasenplaugh, W.2
Qureshi, M.K.3
Sebot, J.4
S Jr., S.C.5
Emer, J.6
-
14
-
-
4644299010
-
A first-order superscalar processor model
-
T. S. Karkhanis and J. E. Smith. A first-order superscalar processor model. In ISCA, 2004.
-
(2004)
ISCA
-
-
Karkhanis, T.S.1
Smith, J.E.2
-
15
-
-
10444238444
-
Fair cache sharing and partitioning in a chip multiprocessor architecture
-
S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning in a chip multiprocessor architecture. In PACT, 2004.
-
(2004)
PACT
-
-
Kim, S.1
Chandra, D.2
Solihin, Y.3
-
16
-
-
33749646951
-
METERG: Measurement-based end-to-end performance estimation technique in QoS-capable multiprocessors
-
J. W. Lee and K. Asanovic. METERG: Measurement-based end-to-end performance estimation technique in QoS-capable multiprocessors. In RTAS, 2006.
-
(2006)
RTAS
-
-
Lee, J.W.1
Asanovic, K.2
-
17
-
-
31944440969
-
Pin: Building customized program analysis tools with dynamic instrumentation
-
C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: building customized program analysis tools with dynamic instrumentation. In PLDI, 2005.
-
(2005)
PLDI
-
-
Luk, C.-K.1
Cohn, R.2
Muth, R.3
Patil, H.4
Klauser, A.5
Lowney, G.6
Wallace, S.7
Reddi, V.J.8
Hazelwood, K.9
-
18
-
-
84962144701
-
Balancing throughput and fairness in SMT processors
-
K. Luo, J. Gummaraju, and M. Franklin. Balancing throughput and fairness in SMT processors. In ISPASS, 2001.
-
(2001)
ISPASS
-
-
Luo, K.1
Gummaraju, J.2
Franklin, M.3
-
19
-
-
0014701246
-
Evaluation techniques for storage hierarchies
-
R. L. Mattson, J. Gecsei, D. R. Slutz, and I. L. Traiger. Evaluation techniques for storage hierarchies. IBM Systems Journal, 9(2):78-117, 1970.
-
(1970)
IBM Systems Journal
, vol.9
, Issue.2
, pp. 78-117
-
-
Mattson, R.L.1
Gecsei, J.2
Slutz, D.R.3
Traiger, I.L.4
-
22
-
-
47349122373
-
Stall-time fair memory access scheduling for chip multiprocessors
-
O. Mutlu and T. Moscibroda. Stall-time fair memory access scheduling for chip multiprocessors. In MICRO, 2007.
-
(2007)
MICRO
-
-
Mutlu, O.1
Moscibroda, T.2
-
25
-
-
77952249144
-
A framework for managing multicore resources
-
K. J. Nesbit, M. Moreto, F. J. Cazorla, A. Ramirez, M. Valero, and J. E. Smith. A framework for managing multicore resources. IEEE Micro, special issue on Interaction of Computer Architecture and Operating System in the Many-core Era, 38(3), 2008.
-
(2008)
IEEE Micro, Special Issue on Interaction of Computer Architecture and Operating System in the Many-core Era
, vol.38
, Issue.3
-
-
Nesbit, K.J.1
Moreto, M.2
Cazorla, F.J.3
Ramirez, A.4
Valero, M.5
Smith, J.E.6
-
26
-
-
34548042910
-
Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches
-
M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO, 2006.
-
(2006)
MICRO
-
-
Qureshi, M.K.1
Patt, Y.N.2
-
27
-
-
34247108325
-
Architectural support for operating system-driven CMP cache management
-
N. Rafique, W.-T. Lim, and M. Thottethodi. Architectural support for operating system-driven CMP cache management. In PACT, 2006.
-
(2006)
PACT
-
-
Rafique, N.1
Lim, W.-T.2
Thottethodi, M.3
-
29
-
-
68949199685
-
A dynamically reconfigurable cache for multithreaded processors
-
A. Settle, D. Connors, E. Gibert, and A. Gonzalez. A dynamically reconfigurable cache for multithreaded processors. Journal of Embedded Computing, 1(3-4), 2005.
-
(2005)
Journal of Embedded Computing
, vol.1
, Issue.3-4
-
-
Settle, A.1
Connors, D.2
Gibert, E.3
Gonzalez, A.4
-
30
-
-
1342324998
-
Discovering and exploiting program phases
-
T. Sherwood, E. Perelman, G. Hamerly, S. Sair, and B. Calder. Discovering and exploiting program phases. IEEE Micro, 2003.
-
(2003)
IEEE Micro
-
-
Sherwood, T.1
Perelman, E.2
Hamerly, G.3
Sair, S.4
Calder, B.5
-
32
-
-
84949769332
-
A new memory monitoring scheme for memory-aware scheduling and partitioning
-
G. E. Suh, S. Devadas, and L. Rudolph. A new memory monitoring scheme for memory-aware scheduling and partitioning. In HPCA, 2002.
-
(2002)
HPCA
-
-
Suh, G.E.1
Devadas, S.2
Rudolph, L.3
-
33
-
-
0029200683
-
Simultaneous multi-threading: Maximizing on-chip parallelism
-
D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous multi-threading: maximizing on-chip parallelism. In ISCA, 1995.
-
(1995)
ISCA
-
-
Tullsen, D.M.1
Eggers, S.J.2
Levy, H.M.3
-
34
-
-
47249121916
-
FAME: Fairly measuring multithreaded architectures
-
J. Vera, F. J. Cazorla, A. Pajuelo, O. J. Santana, E. Fernandez, and M. Valero. FAME: Fairly measuring multithreaded architectures. In PACT, 2007.
-
(2007)
PACT
-
-
Vera, J.1
Cazorla, F.J.2
Pajuelo, A.3
Santana, O.J.4
Fernandez, E.5
Valero, M.6
-
35
-
-
29144463717
-
Fast and fair: Data-stream quality of service
-
T. Y. Yeh and G. Reinman. Fast and fair: data-stream quality of service. In CASES, 2005.
-
(2005)
CASES
-
-
Yeh, T.Y.1
Reinman, G.2
-
36
-
-
12844271066
-
Dynamic tracking of page miss ratio curve for memory management
-
P. Zhou, V. Pandey, J. Sundaresan, A. Raghuraman, Y. Zhou, and S. Kumar. Dynamic tracking of page miss ratio curve for memory management. In ASPLOS, 2004.
-
(2004)
ASPLOS
-
-
Zhou, P.1
Pandey, V.2
Sundaresan, J.3
Raghuraman, A.4
Zhou, Y.5
Kumar, S.6
|