An adaptive shared/private NUCA cache partitioning scheme for chip multiprocessors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2007, Pages 2-12

  Dybdahl, Haakon ^a   Stenström, Per ^b  

^a NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Norway)

^b CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CAPACITY; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION;

CHIP MEMORY BANDWIDTH; NON-UNIFORM CACHE ARCHITECTURES (NUCAS); PARTITION SIZE; PER-CORE PARTITIONS;

BUFFER STORAGE;

EID: 34547670591     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2007.346180     Document Type: Conference Paper

References (15)

1. T. Austin, E. Larson, and D. Ernst. SimpleScalar: An infrastructure for computer system modeling. IEEE Comp., V35I2, 2002.
2. B. M. Beckmann and D. A. Wood. Managing wire delay in large chip-multiprocessor caches. MICRO 37, 2004.
3. J. Chang and G. S. Sohi. Cooperative caching for chip multiprocessors. ISCA, 2006.
4. D. Chiou, P. Jain, S. Devadas, and L. Rudolph. Dynamic cache partitioning via columnization. Proceedings of Design Automation Conference, Los Angeles, 2000.
5. Z. Chishti, M. D. Powell, and T. N. Vijaykumar. Distance associativity for high-performance energy-efficient non-uniform cache architectures. MICRO 36, 2003.
6. Z. Chishti, M. D. Powell, and T. N. Vijaykumar. Optimizing replication, communication, and capacity allocation in CMPs. ISCA, 2005.
7. H. Dybdahl, P. Stenström, and L. Natvig. A cachepartitioning aware replacement policy for chip multiprocessors. HiPC, 2006.
8. J. Huh, C. Kim, H. Shafi, L. Zhang, D. Burger, and S. W. Keckler. A NUCA substrate for flexible CMP cache sharing. ICS, 2005. [9] C. Kim, D. Burger, and S. W. Keckler. Nonuniform cache architectures for wire-delay dominated on-chip caches. IEEE Micro, vol. 23, no. 6, pp. 99-107, 2003.
9. S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning on a chip multiprocessor architecture. Proceedings of the International Conference on Parallel Architecture and Compilation Techniques (PACT), 2004.
10. M. K. Qureshi, D. N. Lynch, O. Mutlu, and Y. N. Patt. A case for mlp-aware cache replacement. ISCA, 2006.
11. J. E. Smith. Characterizing computer performance with a single number. Communications of the ACM, 31(10), 1988.
12. G. Suh, S. Devadas, and L. Rudolph. Dynamic cache partitioning for simultaneous multithreading systems. IASTED Int. Conf. on Parallel and Distributed Computing Systems, 2001.
13. G. E. Suh, S. Devadas, and L. Rudolph. A new memory monitoring scheme for memory-aware scheduling and partitioning. HPCA, 2002.
14. D. Tarjan, S. Thoziyoor, and N. P. Jouppi. Cacti 4.0. Technical report HP Laboratories Palo Alto, HPL-2006-86, 2006.
15. M. Zhang and K. Asanovic. Victim replication: Maximizing capacity while hiding wire delay in tiled chip multiprocessors. ISCA, 2005.