An analytical performance model for co-management of last-level cache and bandwidth sharing

IEEE International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems - Proceedings

Volumn , Issue , 2011, Pages 150-158

  Oh, Taecheol ^a   Lee, Kiyeon ^a   Cho, Sangyeun ^a  

^a University of Pittsburgh   (United States)

Author keywords

Chip multiprocessor (CMP); performance modeling; resource sharing; simulation

Indexed keywords

ANALYTICAL MODEL; ANALYTICAL PERFORMANCE MODEL; BANDWIDTH PARTITIONING; BANDWIDTH RESOURCE; BANDWIDTH SHARING; CACHE CAPACITY; CHIP MULTIPROCESSORS; CO-MANAGEMENT; INTER-DEPENDENCES; OFF-CHIP; OFF-CHIP MEMORIES; OPTIMAL RESOURCE MANAGEMENT; PARTITIONING PROBLEM; PERFORMANCE MODELING; PROCESSOR CORES; RESOURCE SHARING; SIMULATION;

COMPUTER SIMULATION; MATHEMATICAL MODELS; MULTIPROCESSING SYSTEMS; SYSTEMS ANALYSIS; TELECOMMUNICATION SYSTEMS;

BANDWIDTH;

EID: 80053045712     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MASCOTS.2011.17     Document Type: Conference Paper

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