Bank-aware dynamic cache partitioning for multicore architectures

Proceedings of the International Conference on Parallel Processing

Volumn , Issue , 2009, Pages 18-25

  Kaseridis, Dimitris ^a   Stuecheli, Jeffrey ^a,b   John, Lizy K ^a  

^a The University of Texas at Austin   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE DESIGN; CACHE HIERARCHIES; CACHE SCHEME; CHIP-MULTIPROCESSOR; COMPUTATION RESOURCES; COMPUTATIONAL RESOURCES; CORE SYSTEMS; CRITICAL COMPONENT; CYCLE ACCURATE; DESTRUCTIVE INTERFERENCE; DYNAMIC CACHE; DYNAMIC PARTITIONING; FULL SYSTEM SIMULATORS; MULTICORE ARCHITECTURES; SHARED CACHE; SINGLE CHIPS; VIRTUALIZATIONS;

SOFTWARE ARCHITECTURE;

NANOTECHNOLOGY;

EID: 77951427968     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2009.55     Document Type: Conference Paper

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