Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2008, Pages 367-378

  Lin, Jiang ^a   Lu, Qingda ^b   Ding, Xiaoning ^b   Zhang, Zhao ^a   Zhang, Xiaodong ^b   Sadayappan, P ^b  

^a Iowa State University of Science and Technology   (United States)

^b Ohio State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AD HOC NETWORKS; BENCHMARKING; CACHE MEMORY; CHANNEL CAPACITY; COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS; COMPUTER SOFTWARE SELECTION AND EVALUATION; COMPUTERS; QUALITY OF SERVICE;

BENCHMARK SUITES; CACHE PARTITIONING; DYNAMIC BEHAVIORS; GAINING INSIGHTS; HARDWARE DESIGNS; INTERACTION EFFECTS; MEMORY ADDRESS MAPPINGS; MEMORY BANDWIDTHS; MULTICORE; MULTICORE PROCESSORS; OPTIMIZATION OBJECTIVES; PARTITIONING AND SHARING; PERFORMANCE EVALUATIONS; PROGRAM EXECUTIONS; REAL SYSTEMS; SIMULATION TIMES; SOFTWARE APPROACHES; SOFTWARE LAYERS; STATIC AND DYNAMICS;

COMPUTER SOFTWARE;

EID: 57749186047     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2008.4658653     Document Type: Conference Paper

References (21)

1. E. Bugnion, J.M. Anderson, T. C. Mowry, M. Rosenblum, and M. S. Lam. Compiler-directed page coloring for multiprocessors. In Proc. ASPLOS'96, pages 244-255, 1996.
2. J. Chang and G. S. Sohi. Cooperative cache partitioning for chip multiprocessors. In Proc. ICS'07, 2007.
3. S. Cho and L. Jin. Managing distributed, shared L2 caches through OS-level page allocation. In Proc.MICRO'06, pages 455-468, 2006.
4. Hewlett-Packed Development Company. Perfmon project. http://www.hpl.hp.com/research/linux/perfmon.
5. L. R. Hsu, S. K. Reinhardt, R. Iyer, and S. Makineni. Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource. In Proc. PACT'06, pages 13-22, 2006.
6. R. Iyer. CQoS: a framework for enabling qos in shared caches of cmp platforms. In Proc. ICS'04, pages 257-266, 2004.
7. R. Iyer, L. Zhao, F. Guo, Y. Solihin, S. Markineni, D. Newell, R. Illikkal, L. Hsu, and S. Reinhardt. QoS policy and architecture for cache/memory in CMP platforms. In Proc. SIGMETRICS'07, 2007.
8. S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning in a chip multiprocessor architecture. In Proc. PACT'04, pages 111-122, 2004.
9. C. Liu, A. Sivasubramaniam, and M. Kandemir. Organizing the last line of defense before hitting the memory wall for cmps. In Proc. HPCA'04, page 176, 2004.
10. K. J. Nesbit, J. Laudon, and J. E. Smith. Virtual private caches. In Proc. ISCA'07, 2007.
11. M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In Proc. MICRO'06, pages 423-432, 2006.
12. N. Rafique, W.-T. Lim, and M. Thottethodi. Architectural support for operating system-driven CMP cache management. In Proc. PACT'06, pages 2-12, 2006.
13. T. Sherwood, B. Calder, and J. Emer. Reducing cache misses using hardware and software page placement. In Proc. ICS'99, pages 155-164, 1999.
14. A. Snavely, D. M. Tullsen, and G. Voelker. Symbiotic jobscheduling with priorities for a simultaneous multithreading processor. In Proc. ASPLOS'02, pages 66-76, June 2002.
15. G.W. Snedecor and W. G. Cochran. Statistical Methods, pages 172-195. Iowa State University Press, sixth edition, 1967.
16. Standard Performance Evaluation Corporation. SPEC CPU2006. http://www.spec.org.
17. G. E. Suh, S. Devadas, and L. Rudolph. A new memory monitoring scheme for memory-aware scheduling and partitioning. In Proc. HPCA'02, pages 117-128, 2002.
18. G. E. Suh, L. Rudolph, and S. Devadas. Dynamic partitioning of shared cache memory. The Journal of Supercomputing, 28(1):7-26, 2004.
19. D. Tam, R. Azimi, L. Soares, and M. Stumm. Managing shared L2 caches on multicore systems in software. In WIOSCA'07, Jun. 2007.
20. G. Taylor, P. Davies, and M. Farmwald. The TLB slice-a low-cost high-speed address translation mechanism. In Proc. ISCA'90, pages 355-363, 1990.
21. D. M. Tullsen and J. A. Brown. Handling long-latency loads in a simultaneous multithreading processor. In Proc. MICRO'01, pages 318-327, 2001.