MLP-aware dynamic cache partitioning

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4917 LNCS, Issue , 2008, Pages 337-352

  Moreto, Miquel ^a   Cazorla, Francisco J ^b   Ramirez, Alex ^a,b   Valero, Mateo ^a,b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b BARCELONA SUPERCOMPUTING CENTER   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; MICROPROCESSOR CHIPS;

CACHE MISSES; DYNAMIC CACHING; DYNAMIC PARTITIONING; EMBEDDED ARCHITECTURES; FOUR-CORE; HARDWARE COSTS; INTERNATIONAL CONFERENCES; L2 CACHE; MEMORY LATENCIES; MEMORY LEVEL PARALLELISM; MULTITHREADED ARCHITECTURES; PRACTICAL IMPLEMENTATION;

PROGRAM COMPILERS;

EID: 49949085575     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-77560-7_23     Document Type: Conference Paper

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