Analytical cache models with applications to cache partitioning

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2001, Pages 1-12

  Edward Suh, G ^a   Devadas, S ^a   Rudolph, L ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CONTROL; COMPUTER SIMULATION; DATA STRUCTURES; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; ONLINE SYSTEMS; OPTIMIZATION; REAL TIME SYSTEMS; RESOURCE ALLOCATION; SCHEDULING; TIME SHARING PROGRAMS;

CACHE PARTITIONING;

CACHE MEMORY;

EID: 0034826142     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)

1. An analytical cache model
2. Simultaneous multithreading: A platform for next-generation processors
3. Eliminating cache conflict misses through XOR-based placement functions
4. SPEC CPU2000: Measuring CPU performance in the new millennium
5. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
6. Process dependent static cache partitioning for real-time systems
7. Effects of multithreading on cache performance
8. Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading
9. Efficient memory simulation in SimICS
10. The effect of context switches on cache performance
11. Complete computer system simulation: The Sim OS approach
12. Using processor-cache affinity information in shared-memory multiprocessor scheduling
13. Optimal partitioning of cache memory
14. Set-associative cache models for time-shared systems
15. Footprints in the cache
16. Improving disk cache hit-ratios through cache partitioning
17. Randomized cache placement for eleminating conflicts
18. Benefits of cache-affinity scheduling in shared-memory multiprocessors: A summary
19. Simultaneous multithreading: Maximizing on-chip parallelism
20. Trace-driven memory simulation: A survey
21. Performance analysis using the MIPS R1000