Cache latency control for application fairness or differentiation in power-constrained chip multiprocessors

IEEE Transactions on Computers

Volumn 61, Issue 10, 2012, Pages 1371-1385

  Wang, Xiaorui ^a   Ma, Kai ^a   Wang, Yefu ^b  

^a The Ohio State University   (United States)

^b University of Tennessee   (United States)

Author keywords

cache latency; chip multiprocessors; control theory; fairness; performance differentiation; Power capping

Indexed keywords

APPLICATION THREADS; ARCHITECTURAL LEVELS; CACHE ACCESS; CACHE LATENCY; CACHE MANAGEMENT; CACHE SHARING; CHIP MULTIPROCESSOR; CHIP-LEVEL POWER; CONTROL ACCURACY; CONTROL ARCHITECTURE; DYNAMIC CACHE; FAIRNESS; FAIRNESS GUARANTEE; L2 CACHE; LOW-POWER MODE; ON-CHIP CACHE; POWER CAPPING;

CONTROL THEORY; DESIGN; SYSTEM STABILITY;

MULTIPROCESSING SYSTEMS;

EID: 84865689576     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2011.187     Document Type: Article

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