Cache friendliness-aware managementof shared last-level caches for highperformance multi-core systems

IEEE Transactions on Computers

Volumn 63, Issue 4, 2014, Pages 874-887

  Kaseridis, Dimitris ^a   Iqbal, Muhammad Faisal ^a   John, Lizy Kurian ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Cache resource management; chip multiprocessors; last level caches; memory level parallelism

Indexed keywords

MICROPROCESSOR CHIPS;

CACHE MANAGEMENT SCHEMES; CHIP MULTIPROCESSOR; DESTRUCTIVE INTERFERENCE; FULL-SYSTEM SIMULATION; LAST-LEVEL CACHES; MEMORY-LEVEL PARALLELISMS; OUT-OF-ORDER EXECUTION; RESOURCE MANAGEMENT;

CACHE MEMORY;

EID: 84897133868     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2013.18     Document Type: Article

References (34)

1. J. Chang and G.S. Sohi, "Cooperative Cache Partitioning for Chip Multiprocessors, " Proc. Int'l Conf. Supercomputing (ICS), pp. 242-252, 2007. (Pubitemid 47281621)
2. Y. Chou, B. Fahs, and S. Abraham, "Microarchitecture Optimizations for Exploiting Memory-Level Parallelism, " Proc. Int'l Symp. Computer Architecture, pp. 76-88, 2004.
3. F. von Wieser, Der Naturliche Werth [Natural Value]. Book I, chapter V, The Academy of Political Science, 1889.
4. F. Guo et al., "From Chaos to QoS: Case Studies in CMP Resource Management, " Computer Architecture News, vol. 35, pp. 21-30, 2007.
5. E. Herrero et al., "Elastic Cooperative Caching: An Autonomous Dynamically Adaptive Memory Hierarchy for Chip Multiprocessors, " Proc. Int'l Symp. Computer Architecture, pp. 419-428, 2010.
6. L. Hsu, S. Reinhardt, R. Iyer, and S. Makineni, "Communist, Utilitarian, and Capitalist Cache Policies on CMPs: Caches as a Shared Resource, " Proc. 15th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT), pp. 13-22, 2006. (Pubitemid 46601077)
7. R. Iyer et al., "CQOS: A Framework for Enabling QoS in Shared Caches of CMP Platforms, " Proc. Int'l Conf. Supercomputing (ICS), pp. 257-266, 2004.
8. A. Jaleel, W. Hasenplaugh, M. Qureshi, J. Sebot, S. Steely Jr., and J. Emer, "Adaptive Insertion Policies for Managing Shared Caches, " Proc. 17th Int'l Conf. Parallel Architectures and Compilation Techniques (PACT), pp. 208-219, 2008.
9. D. Kaseridis et al., "Bank-Aware Dynamic Cache Partitioning for Multicore Architectures, " Proc. Int'l Conf. Parallel Processing (ICPP), pp. 18-25, 2009.
10. D. Kaseridis et al., "A Bandwidth-Aware Memory-Subsystem Resource Management Using Non-Invasive Resource Profilers for Large CMP Systems, " Proc. 16th Int'l Symp. High Performance Computer Architecture, pp. 93-105, 2010.
11. R. Kessler, R. Jooss, A. Lebeck, and M. Hill, "Inexpensive Imple mentations of Set-Associativity, " Proc. Int'l Symp. Computer Archi tecture (ISCA), pp. 131-139, 1989.
12. R. Kessler, M.D. Hill, and D.A. Wood, "A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches, " IEEE Trans. Computers, vol. 43, no. 6, pp. 664-675, June 1994.
13. S. Kim et al., "Cache Sharing and Partitioning in a Chip Multiprocessor Architecture, " Proc. 13th Int'l Conf. Parallel Architecture and Compilation Techniques (PACT), pp. 111-122, 2004.
14. D. Kroft, "Lockup-Free Instruction Fetch/Prefetch Cache Organization, " Proc. Intl. Symp. Computer Architechture, 1981.
15. K. Luo et al., "Balancing Throughput and Fairness in SMT Processors, " Proc. IEEE Int'l Symp. Performance Analysis of Systems and Software (ISPASS), 2001.
16. R.L. Mattson et al., "Evaluation Techniques for Storage Hierarchies, " IBM Systems J., vol. 9, no. 2, pp. 78-117, 1970.
17. M.M.K. Martin et al., "Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset, " Computer Architecture News, vol. 33, pp. 92-99, Nov. 2005.
18. M. Moreto et al., "MLP-Aware Dynamic Cache Partitioning, " Proc. Third Int'l Conf. High Performance Embedded Architectures and Compilers (HIPEAC), pp. 337-352, 2008.
19. M.K. Qureshi and Y.N. Patt, "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches, " Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO), pp. 423-432, 2006. (Pubitemid 351337015)
20. M.K. Qureshi et al., "Adaptive Insertion Policies for High-Performance Caching, " Proc. 34th Ann. Int'l Symp. Computer Architecture (ISCA), pp. 381-391, 2007. (Pubitemid 47582119)
21. N. Rafique, W. Lim, and M. Hottethodi, "Architectural Support for Operating System-Driven CMP Cache Management, " Proc. 15th Int'l Conf. Parallel Architectures and Compilation Techniques, pp. 2-12, 2006. (Pubitemid 46601076)
22. R. Reddy and P. Petrov, "Cache Partitioning for Energy-Efficient and Interference-Free Embedded Multitasking, " ACM Trans. Embedded Computers and Systems, vol. 9, no. 3, article 16, Feb. 2010.
23. S. Rixner et al., "Memory Access Scheduling, " Proc. Int'l Symp. Computer Architecture, 2000.
24. G.E. Suh et al., "Dynamic Partitioning of Shared Cache Memory, " J. Supercomputing, vol. 28, no. 1, pp. 7-26, 2004.
25. J. Shen et al., Modern Processor Design: Fundamentals of Superscalar Processors. McGraw-Hill Education, 2004.
26. S. Srikantaiah et al., "SHARP Control: Controlled Shared Cache Management in Chip Multiprocessors, " Proc. 42nd Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO 42), 2009.
27. Simics Microarchitect's Toolset, http://www.virtutech.com/, 2014
28. SPEC cpu2006 Benchmark Suit, http://www.spec.org, 2014.
29. H.S. Stone et al., "Optimal Partitioning of Cache Memory, " IEEE Trans. Computers, vol. 41, no. 9, pp. 1054-1068, Sept. 1992.
30. W. Wang et al., "Dynamic Cache Reconfiguration and Partitioning for Energy Optimization in Real-Time Multi-Core Systems, " Proc. 48th Design Automation Conf. (DAC '11), 2011.
31. Y. Xie and G.H. Loh, "PIPP: Promotion/Insertion Pseudo-parti-tioning of Multicore Shared Caches, " Proc. 36th Ann. Int'l Symp. Computer Architecture (ISCA), pp. 174-183, 2009.
32. P. Zhou et al., "Dynamic Tracking of Page Miss Ratio Curve for Memory Management, " Proc. 11th Int'l Conf. Architectural Support for Programming Languages and Operating Systems, pp. 177-188, 2004.
33. L. Zhao et al., "CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms, " Proc. 16th Int'l Conf. Parallel Architecture and Compilation Techniques (PACT), pp. 339-352, 2007.
34. S. Zhuravlev et al., "Addressing Shared Resource Contention in Multicore Processors via Scheduling, " Proc. Architectural Support for Programming Languages and Operating Systems, 2010.