Understanding how off-chip memory bandwidth partitioning in chip multiprocessors affects system performance

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2010, Pages

  Liu, Fang ^a   Jiang, Xiaowei ^a   Solihin, Yan ^a  

^a North Carolina State University   (United States)

Author keywords

Cache partitioning; Chip Multi Processor; Off chip memory bandwidth; Off chip memory bandwidth partitioning; Shared cache

Indexed keywords

ANALYTICAL MODEL; BANDWIDTH PARTITIONING; CACHE PARTITIONING; CHIP-MULTIPROCESSOR; COMPUTING PLATFORM; IN-CHIP; MANY CORE; OFF-CHIP; OFF-CHIP MEMORIES; PERFORMANCE IMPROVEMENTS; SHARED CACHE; SYSTEM DESIGNERS;

BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTERS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY;

CACHE MEMORY;

EID: 77952569781     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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