TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2012, Pages 91-102

  Lee, Jaekyu ^a   Kim, Hyesoon ^a  

^a Georgia Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MANAGEMENT; CACHE MANAGEMENT POLICIES; CACHE MANAGEMENT SCHEMES; CACHE PARTITIONING; DYNAMIC CACHE; HETEROGENEOUS ARCHITECTURES; INTERVAL PREDICTION; MEMORY LATENCIES; NEW MECHANISMS; SHARED CACHE; SHARED RESOURCES; THREAD-LEVEL PARALLELISM;

COMPUTER ARCHITECTURE; PROGRAM PROCESSORS; SUPERCOMPUTERS;

BENCHMARKING;

EID: 84860351946     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2012.6168947     Document Type: Conference Paper

References (29)

1. MacSim. http://code.google.com/p/macsim/.
2. AMD. Fusion. http://sites.amd.com/us/fusion/apu/Pages/fusion.aspx.
3. D. Chang, C. Jenkins, P. Garcia, S. Gilani, P. Aguilera, A. Nagarajan, M. Anderson, M. Kenny, S. Bauer, M. Schulte, and K. Compton. ERCBench: An open-source benchmark suite for embedded and reconfigurable computing. In FPL'10, pages 408-413, 2010.
4. M. Chaudhuri. Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches. In MICRO-42, pages 401-412, 2009.
5. S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, S.-H. Lee, and K. Skadron. Rodinia: A benchmark suite for heterogeneous computing. In IISWC'09, 2009.
6. G. Diamos, A. Kerr, S. Yalamanchili, and N. Clark. Ocelot: A dynamic compiler for bulk-synchronous applications in heterogeneous systems. In PACT-19, 2010.
7. Intel. Sandy Bridge. http://software.intel.com/en-us/articles/sandy- bridge/.
8. A. Jaleel, W. Hasenplaugh, M. Qureshi, J. Sebot, S. Steely, Jr., and J. Emer. Adaptive insertion policies for managing shared caches. In PACT-17, pages 208-219, 2008.
9. A. Jaleel, K. B. Theobald, S. C. Steely, Jr., and J. Emer. High performance cache replacement using re-reference interval prediction (RRIP). In ISCA-32, pages 60-71, 2010.
10. S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning in a chip multiprocessor architecture. In PACT-13, pages 111-122, 2004.
11. M. D. Linderman, J. D. Collins, H. Wang, and T. H. Meng. Merge: a programming model for heterogeneous multi-core systems. In ASPLOS XIII, 2008.
12. F. Liu, X. Jiang, and Y. Solihin. Understanding how offchip memory bandwidth partitioning in chip multiprocessors affects system performance. In HPCA-16, pages 1-12, jan. 2010.
13. M. Moretó, F. J. Cazorla, A. Ramírez, and M. Valero. MLPaware dynamic cache partitioning. In HiPEAC'08, volume 4917, pages 337-352. Springer, 2008.
14. NVIDIA. Fermi: Nvidia's next generation cuda compute architecture. http://www.nvidia.com/fermi.
15. NVIDIA. Project denver. http://blogs.nvidia.com/2011/01/project-denver- processor-to-usher-in-new-era-of-computing/.
16. OpenCL. The open standard for parallel programming of heterogeneous systems. http://www.khronos.org/opencl.
17. H. Patil, R. Cohn, M. Charney, R. Kapoor, A. Sun, and A. Karunanidhi. Pinpointing representative portions of large intel®itanium®programs with dynamic instrumentation. In MICRO-37, pages 81-92, 2004.
18. Pin. A Binary Instrumentation Tool. http://www.pintool.org.
19. M. K. Qureshi, A. Jaleel, Y. N. Patt, S. C. Steely, and J. Emer. Adaptive insertion policies for high performance caching. In ISCA-29, pages 381-391, 2007.
20. M. K. Qureshi, D. N. Lynch, O. Mutlu, and Y. N. Patt. A case for MLP-aware cache replacement. In ISCA-28, pages 167-178, 2006.
21. M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO-39, pages 423-432, 2006.
22. S. Srikantaiah, M. Kandemir, and Q. Wang. Sharp control: Controlled shared cache management in chip multiprocessors. In MICRO-42, pages 517 -528, dec. 2009.
23. G. Suh, S. Devadas, and L. Rudolph. A new memory monitoring scheme for memory-aware scheduling and partitioning. In HPCA-8, pages 117-128, feb. 2002.
24. G. E. Suh, L. Rudolph, and S. Devadas. Dynamic partitioning of shared cache memory. The Journal of Supercomputing, 28(1):7-26, 2004.
25. G. Suo, X. Yang, G. Liu, J. Wu, K. Zeng, B. Zhang, and Y. Lin. IPC-based cache partitioning: An ipc-oriented dynamic shared cache partitioning mechanism. In ICHIT'08, pages 399 -406, aug. 2008.
26. The IMPACT Research Group, UIUC. Parboil benchmark suite. http://impact.crhc.illinois.edu/parboil.php.
27. Y. Xie and G. H. Loh. PIPP: promotion/insertion pseudopartitioning of multi-core shared caches. In ISCA-31, pages 174-183, 2009.
28. Y. Xie and G. H. Loh. Scalable shared-cache management by containing thrashing workloads. In Y. N. Patt, P. Foglia, E. Duesterwald, P. Faraboschi, and X. Martorell, editors, HiPEAC'10, volume 5952, pages 262-276. Springer, 2010.
29. C. Yu and P. Petrov. Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms. In DAC'10, pages 132-137, 2010...