Architectural support for operating system-driven CMP cache management

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2006, Issue , 2006, Pages 2-12

  Rafique, Nauman ^a   Lim, Won Taek ^a   Thottethodi, Mithuna ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Cache; CMP; Fairness; Interface; OS; QoS; Quotas; SLAs

Indexed keywords

CACHE; CACHE MANAGEMENT POLICY; CMP; REACTIVE PERFORMANCE DIFFERENTIATION;

DATA STORAGE EQUIPMENT; INTERFACES (COMPUTER); MULTIPROCESSING SYSTEMS; PROGRAM PROCESSORS; QUALITY OF SERVICE;

COMPUTER OPERATING SYSTEMS;

EID: 34247108325     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1152154.1152160     Document Type: Conference Paper

References (29)

1. Paul Barford and Mark Crovella. Generating Representative Web Workloads for Network and Server Performance Evaluation. Technical Report, Boston, MA, USA, 1997.
2. M. J. Buco, R. N. Chang, L. Z. Luan, C. Ward, J. L. Wolf, and P. S. Yu. Utility Computing SLA Management Based Upon Business Objectives. IBM Systems Journal, 43(1): 159-178, 2004.
3. D. R. Cheriton, A. Gupta, P. D. Boyle, and H. A. Goosen. The VMP Multiprocessor: Initial Experience, Refinements, and Performance Evaluation. In ISCA '88: Proceedings of the 15th Annual International Symposium on Computer architecture, pages 410-421, Los Alamitos, CA, USA, 1988. IEEE Computer Society Press.
4. D. Chiou, P. Jain, S. Devadas, and L. Rudolph. Dynamic Cache Partitioning via Columnization. In Proceedings of Design Automation Conference, Los Angeles, June 2000.
5. Joseph R. Eykholt, Steve R. Kleiman, Steve Barton, Roger Faulkner, Anil Shivalingiah, Mark Smith, Dan Stein, Jim Voll, Mary Weeks, and Dock Williams. Beyond Multiprocessing: Multithreading the SunOS Kernel. In Proceedings of the Summer 1992 USENIX Technical Conference and Exhibition, pages 11-18, San Antontio, TX, USA, 1992.
6. Erik G. Hallnor and Steven K. Reinhardt. A Fully Associative Software-Managed Cache Design. In ISCA '00: Proceedings of the 27tth Annual International Symposium on Computer Architecture, pages 107-116, New York, NY, USA, 2000. ACM Press.
7. Ravi Iyer. CQoS: A Framework for Enabling QoS in Shared Caches of CMP Platforms. In ICS '04: Proceedings of the 18th Annual International Conference on Supercomputing, pages 257-266, New York, NY, USA, 2004. ACM Press.
8. B. Jacob and T. Mudge. Software-Managed Address Translation. In HPCA '97: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture, page 156, Washington, DC, USA, 1997. IEEE Computer Society.
9. Seongbeom Kim, Dhruba Chandra, and Yan Solihin. Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture. In IEEE PACT, pages 111-122, 2004.
10. Poonacha Kongetira, Kathirgamar Aingaran, and Kunle Olukotun. Niagara: A 32-Way Multithreaded Spare Processor. IEEE Micro, 25(2): 21-29, 2005.
11. Chun Liu, Anand Sivasubramaniam, and Mahmut T. Kandemir. Organizing the Last Line of Defense before Hitting the Memory Wall for CMP. In International Symposium on High Performance Computer Architecture, pages 176-185, 2004.
12. P. Machanick, P. Salverda, and L. Pompe. Hardware-Software Trade-Offs in a Direct Rambus Implementation of the RAMpage Memory Hierarchy. In Proc. 8th Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), pages 105-114, San Jose, CA, October 1998.
13. Peter S. Magnusson, Magnus Christensson, Jesper Eskilson, Daniel Forsgren, Gustav Hallberg, Johan Hogberg, Fredik Larsson, Andreas Moestedt, and Bengt Werner. Simics: A Full System Simulation Platform. IEEE Computer, 35(2): 50-58, February 2002.
14. Milo M.K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood. Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset. SIGARCH Computer Architecture News, 2005.
15. Jim Mauro. The Solaris Process Model: Managing Thread Execution and Wait Times in the System Clock Handler, 2000.
16. Kunle Olukotun and Lance Hammond. The Future of Microprocessors. ACM Queue, 3(7), September 2005.
17. M. P. Papazoglou and D. Georgakopoulos. Service-oriented Computing: Introduction . Communications of the ACM, 46(10):24-28, 2003.
18. Moinuddin K. Qureshi, David Thompson, and Yale N. Patt. The V-Way Cache: Demand Based Associativity via Global Replacement. In International Symposium on Computer Architecture, pages 544-555, 2005.
19. Nauman Raflque, Won-Taek Lim, and Mithuna Thottethodi. Architectural Support for Operating System-Driven CMP Cache Management. Technical Report TR ECE 06-11, Purdue University, 2006.
20. Parthasarathy Ranganathan and Norman Jouppi. Enterprise IT Trends and Implications for Architecture Research. In Proceedings of the 11th International Symposium on High-Performance Computer Architecture, pages 253-256, Washington, DC, USA, 2005. IEEE Computer Society.
21. Alex Settle, Dan Connors, Enric Gibert, and Antonio Gonzalez. A Dynamically Reconfigurable Cache for Multithreaded Processors. Journal of Embedded Computing: Special Issue on Single-Chip Multi-core Architectures, December 2005.
22. P. Shivakumar and Norm P. Jouppi. CACTI 3.0: An Integrated Cache Timing, Power and Area Model. Technical Report, 2001.
23. Abraham Silberschatz and Peter B. Galvin. Operating System Concepts. Addison-Wesley, 1998.
24. G. Edward Suh, Srinivas Devadas, and Larry Rudolph. A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. In Proceedings of the 8th International Symposium on High-Performance Computer Architecture, page 117, Washington, DC, USA, 2002. IEEE Computer Society.
25. G. Edward Suh, Larry Rudolph, and Srinivas Devadas. Dynamic Partitioning of Shared Cache Memory. The Journal of Super-computing, 28(1):7-26, 2004.
26. sun.com. Solaris Containers-Resource Management and Solaris Zones. In System Administration Guide.
27. Thomas Y. Yeh and Glenn Reinman. Fast and Fair: Data-stream Quality of Service. In CASES '05: Proceedings of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, pages 237-248, New York, NY, USA, 2005. ACM Press.
28. Li Zhang and Danilo Ardagna. SLA Based Profit Optimization in Autonomic Computing Systems. In Proceedings of the 2nd International Conference on Service Oriented Computing, pages 173-182, New York, NY, USA, 2004. ACM Press.
29. Zhichun Zhu and Zhao Zhang. A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. In Proceedings of 11th International Sysmposium on High Performance Computer Architecture, pages 213-224, 2005.