Cache partitioning for energy-efficient and interference-free embedded multitasking

Transactions on Embedded Computing Systems

Volumn 9, Issue 3, 2010, Pages

  Reddy, Rakesh ^a   Petrov, Peter ^b  

^a InHand Electronics Inc   (United States)

^b UNIVERSITY OF MARYLAND   (United States)

Author keywords

Cache memory; Configurable cache; Embedded multitasking; Low power; WCET

Indexed keywords

CACHE PARTITIONING; CONFIGURABLE; CONFIGURABLE CACHE; DATA CACHES; ENERGY EFFICIENT; LARGE PARTS; LARGE STRUCTURES; LEAKAGE POWER; LOW POWER; MEMORY BANDWIDTHS; MULTITASKING ENVIRONMENTS; NANOMETER TECHNOLOGY; OFF-LINE ALGORITHM; PREEMPTIVE MULTITASKING;

EMBEDDED SYSTEMS; MULTITASKING;

CACHE MEMORY;

EID: 77949462086     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/1698772.1698774     Document Type: Article

References (39)

1. AGARWAL, A., HENNESSY, J., AND HOROWITZ, M. 1988. Cache performance of operating system and multiprogramming workloads. ACM Trans. Comput. Syst. 6, 4, 393-431.
2. ALBONESI,D.H. 1999. Selective cache ways: On-demand cache resource allocation. In Proceedings of the International Symposium on Microarchitecture (MICRO'99). IEEE, Los Alamitos, CA, 248-259.
3. ALT, M., FERDINAND, C.,MARTIN, F., ANDWILHELM, R. 1996. Cache behaviour prediction by abstract interpretation. In Proceedings of the Static Analysis Symposium (SAS'96). Springer, Berlin, 52-66. ARM LTD. ARM920T Technical Reference Manual. ARM Ltd.
4. ARNOLD, R., MUELLER, F., WHALLEY, D., AND HARMON, M. 1994. Bounding worst-case instruction cache performance. In Proceedings of the Real-Time Systems Symposium (RTSS'94). IEEE, Los Alamitos, CA, 172-181.
5. AUSTIN, T., LARSON, E., AND ERNST, D. 2002. Simple scalar: An infrastructure for computer system modeling. IEEE Comput. 35, 2, 59-67.
6. CEKLEOV, M. AND DUBOIS, M. 1997. Virtual-address caches part 1: Problems and solutions in uniprocessors. IEEE Micro. 17, 5, 64-71.
7. CHANDRA, D., GUO, F., KIM, S., AND SOLIHIN, Y. 2005. Predicting inter-thread cache contention on a chip multiprocessor architecture. In Proceedings of the International Symposium on High- Performance Computer Architecture (HPCA'05). IEEE, Los Alamitos, CA.
8. CHEN, H.-C. AND CHIANG, J.-S. 2001. A highly configurable cache architecture for embedded systems. In Proceedings of the IEEE Conference on Communications, Computers and Signal Processing (PACRIM). IEEE, Los Alamitos, CA, 315-318.
9. CHIOU, D., JAIN, P., RUDOLPH, L., AND DEVADAS, S. 2000. Application-specific memory management for embedded systems using software-controlled caches. In Proceedings of the Design Automation Conference (DAC'00). ACM, New York, 416-419.
10. FLAUTNER, K., KIM, N., MARTIN, S., BLAAUW, D., AND MUDGE, T. 2002. Drowsy caches: Simple techniques for reducing leakage power. In Proceedings of the International Symposium on Computer Architecture (ISCA'02). ACM, New York, 148-157.
11. GORDON-ROSS, A. ANDVAHID, F. 2007. Aself-tuning configurable cache. In Proceedings of the Design Automation Conference (DAC'07). ACM, New York, 234-237.
12. HECKMANN, R., LANGENBACH, M., THESING, S., AND WILHELM, R. 2003. The influence of processor architecture on the design and the results of wcet tools. In Proceedings of the IEEE 91, 7, 1038-1054.
13. HU, J., KANDEMIR, M., VIJAYKRISHNAN, N., AND IRWIN, M. J. 2005. Analyzing data reuse for cache reconfiguration. ACM Trans. Embedded Comput. Syst. 4, 4, 851-876. INTEL CORPORATION. Intel XScale Microarchitecture. Intel Corporation.
14. KIM, N., FLAUTNER, K., BLAAUW, D., AND MUDGE, T. 2002. Drowsy instruction caches, leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. In Proceedings of the International Symposium on Microarchitecture (MICRO'02). IEEE, Los Alamitos, CA, 219-230.
15. KIM, N. S., FLAUTNER, K., BLAAUW, D., AND MUDGE, T. 2004. Single-vdd and single-vt super- drowsy techniques for low-leakage high-performance instruction caches. In Proceedings of the International Symposium on Low-Power Electronics and Design (ISLPED'04). IEEE, Los Alamitos, CA, 54-57.
16. KIRK, D. 1989. Smart (strategic memory allocation for real-time) cache design. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 229-237.
17. KIRNER, R. AND PUSCHNER, P. 2001. Transformation of path information for wcet analysis during compilation. In Proceedings of the Euromicro Conference on Real-Time Systems (ECRTS'01). IEEE, Los Alamitos, CA, 29.
18. LEE, C., POTKONJAK, M., AND MANGIONE-SMITH, W. H. 1997. Media bench: A tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the International Symposium on Microarchitecture (MICRO'97). IEEE, Los Alamitos, CA, 330-335.
19. LI, Y. S., MALIK, S., AND WOLFE., A. 1997. Cache modeling for real-time software. In Proceedings of the IEEE Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 148-157.
20. MALIK, A., MOYER, B., AND CERMAK, D. 2000. A low-power unified cache architecture providing power and performance flexibility. In Proceedings of the International Symposium on Low-Power Electronics and Design (ISLPED'00). IEEE, Los Alamitos, CA, 241-243.
21. MOGUL, J. AND BORG, A. 1991. The effect of context switches on cache performance. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'91). ACM, New York, 75-84.
22. MUELLER, F. 1995. Compiler support for software-based cache partitioning. In Proceedings of the ACMSIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'95). ACM, New York, 125-133.
23. POWELL, M., YANG, S.-H., FALSAFI, B., ROY, K., AND VIJAYKUMAR, T. N. 2000. Gated-vdd: A circuit technique to reduce leakage in deep-submicron cache memories. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'00). IEEE, Los Alamitos, CA, 90-95.
24. POWELL, M., YANG, S.-H., FALSAFI, B., ROY, K., AND VIJAYKUMAR, T. N. 2001. An integrated circuit/ architecture approach to reducing leakage in deep-submicron high-performance i-caches. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA). IEEE, Los Alamitos, CA, 147-157.
25. QURESHI, M., JALEEL, A., PATT, Y., STEELY, S., AND EMER, J. 2007. Adaptive insertion policies for highperformance caching. In Proceedings of the International Symposium on Computer Architecture (ISCA'07). IEEE, Los Alamitos, CA, 381-391.
26. QURESHI, M. AND PATT, Y. 2006. Utility-based cache partitioning: A low-overhead, highperformance, runtime mechanism to partition shared caches. In Proceedings of the International Symposium on Microarchitecture (MICRO'06). IEEE, Los Alamitos, CA, 423-432.
27. STARNER, J. AND ASPLUND, L. 2004. Measuring the cache interference cost in preemptive real-time systems. In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04). ACM, New York, 146-154.
28. STASCHULAT, J. AND ERNST, R. 2006. Worst-case timing analysis of input dependent data cache behavior. In Proceedings of the Euromicro Conference on Real-Time Systems (ECRTS'06). IEEE, Los Alamitos, CA, 227-236.
29. STASCHULAT, J. AND ERNST, R. 2007. Scalable precision cache analysis for real-time software. ACM Trans. Embedded Comput. Syst. 6, 4, 25.
30. SUH, G., DEVADAS, S., AND RUDOLPH, L. 2002. A new memory monitoring scheme for memoryaware scheduling and partitioning. In Proceedings of the 8th International Symposium on High- Performance Computer Architecture (HPCA'02). IEEE, Los Alamitos, CA, 117-128.
31. TAN, Y. AND MOONEY, I., V. J. 2005. Wcrt analysis for a uniprocessor with a unified prioritized cache. In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05). ACM, New York, 175-182.
32. TANAKA, K. 2003. Fast context switching by hierarchical task allocation and reconfigurable cache. In Proceedings of the Innovative Architecture of Future Generation High-Performance Processors and Systems (IWIA'03). IEEE, Los Alamitos, CA.
33. THOZIYOOR, S., MURALIMANOHAR, N., AHN, J., AND JOUPPI, N. 2008. Cacti 5.1. Tech. rep., HP Laboratories Palo Alto. April.
34. VERA, X., LISPER, B., AND JINGLING, X. 2003. Data caches in multitasking hard real-time systems. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 145-165.
35. WANG, S. AND WANG, L. 2006. Thread-associative memory for multicore and multithreaded computing. In Proceedings of the International Symposium on Low-Power Electronics and Design (ISLPED'06). IEEE, Los Alamitos, CA, 139-142.
36. WOLFE, A. 1994. Software-based cache partitioning for real-time applications. J. Comput. Software Eng. 2, 3, 315-327.
37. YANG, S.-H., FALSAFI, B., POWELL, M. D., AND VIJAYKUMAR, T. N. 2002. Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay. In Proceedings of the 8th International Symposium on High-Performance Computer Architecture (HPCA'02). IEEE, Los Alamitos, CA, 151.
38. ZHANG, C., VAHID, F., AND LYSECKY, R. 2004. A self-tuning cache architecture for embedded systems. ACM Trans. Embedded Comput. Syst. 3, 2, 407-425.
39. ZHANG, C., VAHID, F., AND NAJJAR,W. 2003. A highly configurable cache architecture for embedded systems. In Proceedings of the International Symposium on Computer Architecture (ISCA'03). IEEE, Los Alamitos, CA, 136-146.