Managing shared last-level cache in a heterogeneous multicore processor

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2013, Pages 225-234

  Mekkat, Vineeth ^a   Holey, Anup ^a   Yew, Pen Chung ^a   Zhai, Antonia ^a  

^a University of Minnesota   (United States)

Author keywords

cache management policy; heterogeneous multicores; shared last level cache

Indexed keywords

CACHE MANAGEMENT POLICIES; HETEROGENEOUS MULTI-CORES; HETEROGENEOUS MULTICORE PROCESSORS; LAST-LEVEL CACHES; LASTLEVEL CACHES (LLC); MEMORY ACCESS LATENCY; PERFORMANCE DEGRADATION; THREAD LEVEL PARALLELISM;

PARALLEL ARCHITECTURES;

PARALLEL PROCESSING SYSTEMS;

EID: 84887456430     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2013.6618819     Document Type: Conference Paper

References (27)

1. AMD Accelerated Parallel Processing (APP) Software Development Kit (SDK) http://developer. amd. com/sdks/amdappsdk/.
2. ADVANCED MICRO DEVICES INCORPORATED. Evergreen Family Instruction Set Architecture http://goo. gl/WQ5lE.
3. BROOKWOOD, N. AMD Fusion Family of APUs: Enabling a Superior, Immersive PC Experience. AMD White Paper (2010).
4. HAMERLY, G., PERELMAN, E., LAU, J., AND CALDER, B. Simpoint 3. 0: Faster and more flexible program analysis. In Journal of Instruction Level Parallelism (2005).
5. INTEL CORPORATION. Intel Sandy Bridge Microarchitecture. http://www. intel. com.
6. JALEEL, A., THEOBALD, K. B., STEELY, JR., S. C., AND EMER, J. High performance cache replacement using re-reference interval prediction (RRIP). In ISCA (2010).
7. JOHNSON, T., CONNORS, D., MERTEN, M., AND HWU, W.-M. Runtime cache bypassing. IEEE Transactions on Computers (1999).
8. KHAN, S. M., TIAN, Y., AND JIMENEZ, D. A. Sampling dead block prediction for last-level caches. In MICRO (2010).
9. KHARBUTLI, M., AND SOLIHIN, Y. Counter-based cache replacement and bypassing algorithms. IEEE Transactions on Computers (2008).
10. KHRONOS GROUP. OpenCL-The open standard for parallel programming of heterogeneous systems. http://www. khronos. org/opencl/.
11. KIM, S., CHANDRA, D., AND SOLIHIN, Y. Fair cache sharing and partitioning in a chip multiprocessor architecture. In PACT (2004).
12. LAI, A.-C., FIDE, C., AND FALSAFI, B. Dead-block prediction & deadblock correlating prefetchers. In ISCA (2001).
13. LEE, J., AND KIM, H. TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture. In HPCA (2012).
14. LI, S., AHN, J. H., STRONG, R. D., BROCKMAN, J. B., TULLSEN, D. M., AND JOUPPI, N. P. Mcpat: an integrated power, area, and timing modeling framework for multicore and manycore architectures. In MICRO (2009).
15. LIU, H., FERDMAN, M., HUH, J., AND BURGER, D. Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency. In MICRO (2008).
16. MORETO, M., CAZORLA, F., RAMIREZ, A., AND VALERO, M. Mlpaware dynamic cache partitioning. In HiPEAC. 2008.
17. NVIDIA CORPORATION. NVIDIA CUDA C Programming Guide. http://www. nvidia. com.
18. NVIDIA CORPORATION. Nvidia Project Denver. http://goo. gl/Sbjbb.
19. QURESHI,M. K., JALEEL, A., PATT, Y. N., STEELY, S. C., AND EMER, J. Adaptive insertion policies for high performance caching. In ISCA (2007).
20. QURESHI, M. K., LYNCH, D. N.,MUTLU, O., AND PATT, Y. N. A case for mlp-aware cache replacement. In ISCA (2006).
21. QURESHI, M. K., AND PATT, Y. N. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In MICRO (2006).
22. SALAPURA, V., BLUMRICH, M., AND GARA, A. Design and implementation of the Blue Gene/P snoop filter. In HPCA (2008).
23. SPRADLING, C. D. SPEC CPU2006 Benchmark Tools. SIGARCH Computer Architecture News (2007).
24. SUH, G., RUDOLPH, L., AND DEVADAS, S. Dynamic partitioning of shared cache memory. The Journal of Supercomputing (2004).
25. UBAL, R., JANG, B., MISTRY, P., SCHAA, D., AND KAELI, D. Multi2Sim: A Simulation Framework for CPU-GPU Computing In PACT (2012).
26. XIE, Y., AND LOH, G. H. Pipp: promotion/insertion pseudo-partitioning of multi-core shared caches. In ISCA (2009).
27. XIE, Y., AND LOH, G. H. Scalable shared-cache management by containing thrashing workloads. In HiPEAC (2010).