Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms

Proceedings - Design Automation Conference

Volumn , Issue , 2010, Pages 132-137

  Yu, Chenjie ^a   Petrov, Peter ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

L2 Cache Partitioning; Off Chip bandwidth reduction

Indexed keywords

BANDWIDTH DEMAND; CACHE MISS; CACHE MISS RATES; CACHE PARTITIONING; CACHE UTILIZATION; L2 CACHE; MEMORY BANDWIDTHS; MULTI-CORE PLATFORMS; MULTI-CORE SYSTEMS; MULTITHREADED; OFF-CHIP; OFF-CHIP MEMORIES; POWER CONSUMPTION; PROCESSOR CORES; SERVICE SPEED; SHARED CACHE; SYSTEM BANDWIDTH; TARGET WORKLOADS;

BANDWIDTH; COMPUTER AIDED DESIGN; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; OPTIMIZATION;

CACHE MEMORY;

EID: 77956204832     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1837274.1837309     Document Type: Conference Paper

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